Fuse logic to perform selectively enabled ecc decoding
AssigneeMicron Technology, Inc.
InventorBeau D. Barry
Life of this patent
Estimating the term…
Abstract
Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.
Claims16
A method, comprising:
- receiving first redundancy data having a first number of bits and second redundancy data having a second number of bits from a plurality of fuses based at least in part on a first stage of processing;
- providing the first redundancy data and the second redundancy data to one or more latch circuits based at least in part on the first stage of processing;
- receiving third redundancy data having the first number of bits based at least in part on a second stage of processing that occurs after the first stage of processing;
- receiving error correction code (ECC) data having the second number of bits based at least in part on the second stage of processing;
- and
- performing an ECC operation on the third redundancy data using the ECC data if an error is detected using the ECC data.
An apparatus, comprising:
- an error correction code (ECC) logic circuit configured to:
- in a first mode, be disabled, the first mode indicated by an enable signal indicating a first stage of processing, and
- in a second mode indicated by the enable signal indicating a second stage of processing that occurs after the first stage of processing:
- receive first redundancy data,
- receive second data, the second data being ECC data in the second mode, and
- perform an ECC operation on the first redundancy data based at least in part on the second data to provide corrected first redundancy data;
- a first multiplexer configured to:
- in the first mode:
- receive the first redundancy data, and
- provide the first redundancy data,
- in the second mode:
- receive the corrected first redundancy data, and
- provide the corrected first redundancy data;
- and
- a first fuse latch circuit configured to receive the first redundancy data in the first mode, and receive the corrected first redundancy data in the second mode to selectively replace a first group of defective memory cells.
Dependencies are inferred from the claim text.