Throughput efficient Reed-Solomon forward error correction decoding

A decoder circuit configured to:

• receive a first portion of a first codeword during a plurality of first non-overlap clock cycles;
• receive a second portion of the first codeword and a first portion of a second codeword during an overlap clock cycle between the first plurality of non-overlap clock cycles and a second plurality of non-overlap clock cycles;
• receive a second portion of the second codeword over the second plurality of non-overlap clock cycles;
• and
• compute a first decoded message and a second decoded message from the first codeword and the second codeword, the first decoded message and the second decoded message being output during a period having a length equal to a sum of the first plurality of non-overlap clock cycles, the overlap clock cycle, and the second plurality of non-overlap clock cycles.

A non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to generate a digital representation of an integrated circuit configured to:

• receive a first portion of a first codeword during a plurality of first non-overlap clock cycles;
• receive a second portion of the first codeword and a first portion of a second codeword during an overlap clock cycle between the first plurality of non-overlap clock cycles and a second plurality of non-overlap clock cycles;
• receive a second portion of the second codeword over the second plurality of non-overlap clock cycles;
• and
• compute a first decoded message and a second decoded message from the first codeword and the second codeword, the first decoded message and the second decoded message being output during a period having a length equal to a sum of the first plurality of non-overlap clock cycles, the overlap clock cycle, and the second plurality of non-overlap clock cycles.