Optimizing place-and-routing using a random normalized polish expression

A method comprising:

• generating a first random normalized polish expression;
• using at least one computer processor and the first random normalized polish expression, generating a first place-and-route placement of cells for an integrated circuit design at least by placing a cell adjacent to a separate cell along a first direction and a second direction, wherein the first and the second directions are determined based at least in part upon an operator in the first random normalized polish expression;
• for the first place-and-route placement, generating a plurality of interconnect routing paths between the cells of the first place-and-route placement according to at least the first and the second directions, wherein one or more of the plurality of interconnect routing paths are able to span across different interconnect layers;
• and
• determining respective costs for the interconnect routing paths for the first place-and-route placement, wherein the plurality of interconnect routing paths comprise respective place-and-route solutions,
• wherein a first respective place-and-route solution comprises at least one first interconnect line formed in a gap between a first cell and second cell,
• a second respective place-and-route solution comprises at least one second interconnect line having a 90-degree turn coupling the first and the second cells, and
• a third respective place-and-route solution comprises at least one third interconnect line having at least two 90-degree turns coupling the first and the second cells, and
• calculating respective cost functions for the first, the second, and the third place-and-route solutions;
• based at least in part upon the respective cost functions, selecting one of the first, the second, and the third place-and-route solutions.

A method comprising:

• generating a first random normalized polish expression;
• using at least one computer processor, using the first random normalized polish expression, generating a first place-and-route placement of cells for an integrated circuit design at least by placing a cell adjacent to a separate cell along a first direction and a second direction, wherein the first and the second directions are determined based at least in part upon an operator in the first random normalized polish expression;
• for the first place-and-route placement, generating a plurality of interconnect routing paths between the cells of the first place-and-route placement according to at least the first and the second directions, wherein one or more interconnect routing paths on are able to span across different interconnect layers;
• determining respective interconnection costs for the plurality of interconnect routing paths for the first place-and-route placement, wherein the plurality of interconnect routing paths comprise respective place-and-route solutions;
• generating a second random normalized polish expression;
• using the at least one computer processor and the second random normalized polish expression, generating a second place-and-route solution for the integrated circuit design and a solution cost of the first place-and-route solution, wherein the solution cost is generated based at least in part on a wire length of an interconnect in a space between two cells;
• and
• placing at least two of the cells for the second place-and-route solution adjacent to each other in another direction based at least in part on the second random normalized polish expression.