Phase-locked loop circuit and operation method thereof

A phase-locked loop circuit, comprising:

• a voltage controlled oscillator (VCO) configured to generate a VCO clock of any frequency in response to a voltage control signal;
• a divider configured to divide the VCO clock based on a dividing ratio to output a division clock;
• a phase-frequency error detector configured to receive a reference clock and output a first error compensation signal based on the reference clock and the division clock;
• a sampler configured to receive the reference clock and oversample the reference clock at a rising edge or a falling edge of the VCO clock to output a sampling clock;
• a window phase error detector configured to receive the reference clock and output a second error compensation signal based on the reference clock and the sampling clock;
• a residue phase error detector configured to output a third error compensation signal based on the VCO clock and the sampling clock;
• an adder configured to accumulate the first error compensation signal, the second error compensation signal, and the third error compensation signal to output a final error compensation signal;
• and
• a loop filter configured to convert and output the final error compensation signal into the voltage control signal.