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AssigneeUniversity College Dublin, National University of Ireland
InventorsYizhe Hu, Teerachot Siriburanon, Robert Bodgan Staszewski
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The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.
A phase-locked loop (PLL) for charge-sharing locking, the PLL comprising:
A method of charge-sharing locking for use in a PLL, the method comprising:
A phase-locked loop (PLL) for charge-sharing locking, the PLL comprising:
A method of charge-sharing locking for use in a PLL, the method comprising:
Dependencies are inferred from the claim text.