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US 12,027,599 B2Granted
Single structure CASCODE device and method of manufacturing same
AssigneePostech Research and Business Development Foundation
InventorsRock Hyun Baek, Jun Sik Yoon
Life of this patent
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Abstract
Disclosed in a CASCODE device in which multiple transistors are stacked in a vertical direction and connected in series. The CASCODE device exhibits improvements in device/circuit intrinsic gain (GmRo) that is a performance index for analog/RF applications, cutoff frequency (Ft), and maximum oscillation frequency (Fmax). A method of manufacturing the CASCODE device is also disclosed.
Claims17
A single structure CASCODE device, comprising:
- a substrate;
- a plurality of channels spaced from each other and arranged on the substrate in a vertical direction;
- source and drain regions formed along first and second side surfaces of the plurality of channels;
- a replacement metal gate having a multilayer structure disposed between each of the plurality of channels and formed on a gate oxide layer,
- wherein in the source and drain regions, an upper portion and a lower portion arranged in a vertical direction are isolated from each other by at least one isolation insulating film transversely embedded therein, and
- wherein the replacement metal gate has the multilayer structure in which multiple work function metal layers are stacked on the gate oxide layer,
- wherein, among the multiple work function metal layers, a first work function metal layer formed in a lower channel region and a second work function metal layer formed in an upper channel region have different work functions.
4 more elements
A method of manufacturing a single structure CASCODE device, the method comprising:
- forming a plurality of channels spaced from each other and arranged in a vertical direction on a substrate;
- forming a source/drain region adjacent to the plurality of channels;
- and forming a replacement metal gate between each of the plurality of channels,
- wherein the source/drain region is formed to be in contact with a lower channel region or an upper channel region through a selective epitaxial growth (SEG) process, wherein a step of forming an isolation insulating film is performed at least one time during the forming the source/drain region, and
- the replacement metal gate is formed by performing an etching process to form a gate opening and to expose the plurality of channels, and forming a gate oxide layer and multiple work function metal layers between each of the plurality of channels and in the gate opening, wherein the multiple work function metal layers have different work functions to correspond to the lower channel region and the upper channel region.
2 more elements
Dependencies are inferred from the claim text.