US 12,027,535 B2Granted

Semiconductor device with a capacitor and a plurality of overlapping openings in the conductive layers

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorAtsushi Umezaki

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Abstract

The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

Claims6

Dependent claims

A semiconductor device comprising:

a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
and
a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a first electrode of the capacitor,
wherein a gate of the first transistor is electrically connected to a second electrode of the capacitor,
wherein the gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the first transistor,
wherein the first transistor and the capacitor comprise a first conductive layer and a second conductive layer,
wherein the first conductive layer comprises a region serving as the source or the drain of the first transistor and a region serving as the first electrode of the capacitor,
wherein the second conductive layer comprises a region serving as the gate of the first transistor and a region serving as the second electrode of the capacitor,
wherein the first conductive layer comprises a plurality of first openings,
wherein the second conductive layer comprises a plurality of second openings, and
wherein each of the plurality of first openings has a region that overlaps with the respective one of the plurality of second openings in a plane view.

20 more elements

A semiconductor device comprising:

a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
and
a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a first electrode of the capacitor,
wherein a gate of the first transistor is electrically connected to a second electrode of the capacitor,
wherein the gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the first transistor,
wherein the first transistor and the capacitor comprise a first conductive layer and a second conductive layer,
wherein the first conductive layer comprises a region serving as the source or the drain of the first transistor and a region serving as the first electrode of the capacitor,
wherein the second conductive layer comprises a region serving as the gate of the first transistor and a region serving as the second electrode of the capacitor,
wherein the first conductive layer comprises a first opening,
wherein the second conductive layer comprises a second opening, and
wherein an edge of the second opening is located inside the first opening in a plane view.

20 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/830,675Filed 26 Mar 2020 · continuation
Priority: JP 2014-15053224 Jul 2014
Published: US 2020/0243569 A130 Jul 2020
Granted: 2 Jul 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
H10D 86/441
Characterised by multiple TFTs: interconnections, e.g. scanning lines
H10D 86/481
Characterised by multiple TFTs: integrated with passive devices, e.g. auxiliary capacitors

Family

Application14/804,772Parent of this continuation · filed 21 Jul 2015
Application15/632,704Parent of this continuation · filed 26 Jun 2017
US 2020/0243569 A1Pre-grant publication · published 30 Jul 2020
US 10,608,015 B2Parent of this continuation
US 2016/0027810 A1Published application
US 2017/0294458 A1Published application
US 12,027,535 B2This patent

From the US filing history. Foreign family members aren’t listed.