Subtractively patterned interconnect structures for integrated circuits

An IC structure, wherein the IC structure comprises:

• a plurality of transistors;
• and
• an interconnect structure coupled to the transistors, wherein the interconnect structure comprises:
• a via and a dielectric material adjacent to the via;
• a line in contact with the via, wherein the line extends over the dielectric material, and a top width of the line is smaller than a bottom width of the line;
• and
• a barrier material on a sidewall of the line and between the sidewall of the line and the dielectric material, wherein the barrier material comprises a metal and a chalcogen.

A method of forming an integrated circuit (IC) interconnect structure, the method comprising:

• depositing a metal over a substrate comprising a plurality of transistors and interconnect vias;
• forming interconnect lines coupled through the interconnect vias to the transistors by etching a portion of the metal;
• forming at least one of graphene or a metal chalcogenide in contact with a sidewall of the interconnect lines, but absent from the interconnect vias;
• and
• depositing a dielectric material over the interconnect features.