Data driver and display device having same

A display device comprising:

• a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines;
• a gate driver configured to generate a plurality of gate signals and apply the plurality of gate signals to the plurality of gate lines;
• a plurality of data driving chips configured to generate a plurality of data voltages based on image signal data and apply the plurality of data voltages to the plurality of data lines;
• and
• a signal controller configured to control the gate driver and the data driving chip and generate the image signal data based on image data,
• wherein each of the data driving chips includes:
• a digital to analog converter configured to convert the image signal data for a row of pixels into first data voltages and second data voltages;
• an output buffer including a first output block and a second output block which are commonly connected to the digital to analog converter, the first output block connected to a plurality of first data lines among the data lines and including a plurality of first channels and the second output block connected to a plurality of second data lines among the data lines and including a plurality of second channels;
• and
• only one delay clock generator commonly and directly connected to the first and second output blocks to provide a plurality of first delay clock signals to the first output block and a plurality of second delay clock signals to the second output block,
• wherein the plurality of first delay clock signals have a first phase difference and the plurality of second delay clock signals have a second phase difference different from the first phase difference,
• wherein the first data voltages outputted from the first output block through the first channels are delayed with a first time difference, and
• wherein the second data voltages outputted from the second output block through the second channels are delayed with a second time difference which is different from the first time difference.

A display device comprising:

• a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines;
• a gate driver configured to generate a plurality of gate signals and apply the plurality of gate signals to the plurality of gate lines;
• and
• a plurality of data driving chips configured to generate a plurality of data voltages based on image signal data and apply the plurality of data voltages to the plurality of data lines,
• wherein each of the plurality of data driving chips includes:
• a digital to analog converter configured to convert the image signal data for a row of pixels into first data voltages, second data voltages, and third data voltages;
• an output buffer including a first output block, a second output block, and a third output block which are commonly connected to the digital to analog converter, the first output block connected to a plurality of first data lines among the data lines and including a plurality of first channels, the second output block connected to a plurality of second data lines among the data lines and including a plurality of second channels, the third output block connected to a plurality of third data lines among the data lines and including a plurality of third channels;
• and
• only one delay clock generator commonly and directly connected to the first to third output blocks to provide a plurality of first delay clock signals to the first output block, a plurality of second delay clock signals to the second output block and a plurality of third delay clock signals to the third output block,
• wherein the plurality of first delay clock signals have a first phase difference, the plurality of second delay clock signals have a second phase difference different from the first phase difference, and the plurality of third delay clock signals does not have phase difference,
• wherein the first data voltages outputted from the first output block through the first channels are delayed with a first time difference,
• wherein the second data voltages outputted from the second output block through the second channels are delayed with a second time difference which is different from the first time difference, and
• wherein the third data voltages outputted from the third output block through the third channels have an equal first delay value.