Method and system for repairing memory device

A system for repairing a memory device, comprising

• a detection circuit, configured to perform error detection on memory units of the memory device and output unit addresses of error units, and the error units are damaged memory units;
• a register circuit, electrically connected with the detection circuit and comprising a number of registers, the number being not less than a first preset number, wherein a respective one of the registers is configured to receive a unit address of each of the error units and output a row address of each of the error units, each of the error units occupies the respective one of the registers, and each of the unit addresses comprises a row address;
• a control circuit, electrically connected with the registers and configured to successively select one of the registers, as a target register, in response to a number of the error units detected by the detection circuit reaching the first preset number;
• a reference storage circuit, configured to store and output a repaired row address or an unrepaired row address;
• a first determination circuit, electrically connected with the reference storage circuit and the register circuit, wherein the first determination circuit is configured to receive a row address output by the target register and a row address output by the reference storage circuit, to determine whether the row address in the target register exists in the reference storage circuit, and the first determination circuit is further configured to output a result of the determination;
• and
• a repairing circuit, electrically connected with the first determination circuit, and configured to repair error units that are not repaired through the row address according to the result of the determination,
• wherein the control circuit comprises a first control unit and n switch units, each of the n switch units corresponding to the respective one of the registers, and n is a positive integer greater than 1;
• wherein the first control unit respectively inputs control signals S1-Sn to the n switch units, wherein a control signal input by the first control unit to a kth switch unit is Sk, and k is greater than or equal to 1, or less than or equal to n;
• and in response to any one of the control signals S1-Sn being a high-level signal, remaining control signals are low-level signals;
• and
• wherein in response to the detection circuit detecting that the number of the error units detected by the detection circuit reaches the first preset number, the control signals S1-Sn controlled by the first control unit are successively high-level signals, and then a first switch unit to an nth switch unit are opened in order, so that each of registers corresponding to the first switch unit to the nth switch unit successively becomes the target register, the target register being connected with the first determination circuit.