Circuit structure to measure outliers of process variation effects

An integrated circuit for testing one or more transistors, the integrated circuit comprising:

• a plurality of ring oscillator macro circuits, wherein each ring oscillator macro circuit includes:
• two ring oscillators, wherein each ring oscillator includes an odd number of inverter stages, wherein the inverter stages include the one or more transistors, wherein each ring oscillator is associated with an output signal;
• a first multiplexer configured to receive the output signals associated with the two ring oscillators and provide as an output one of the output signals associated with the two ring oscillators;
• and
• a first divide-by-two circuit, wherein the first divide-by-two circuit is configured to receive the output from the first multiplexer and provide an oscillating signal that is at half of the frequency of the output from the first multiplexer;
• a multiplexer stage including a plurality of multiplexers, wherein each multiplexer of the multiplexer stage is configured to receive an output from a corresponding ring oscillator macro circuit;
• a divide-by-two circuit stage including a plurality of divide-by-two circuits, wherein each divide-by-two circuit is configured to receive an output from each of the multiplexers of the multiplexer stage;
• a second multiplexer configured to receive an output from each of the divide-by-two circuits in the divide-by-two circuit stage;
• a second divide-by-two circuit configured to receive an output from the second multiplexer;
• and
• a frequency measurement circuit configured to measure the frequency of an output from the second divide-by-two circuit.