Neural network processing method and server and electrical device therefor

A server for processing a neural network, comprising:

• a transmission circuit;
• a processor, configured to transform an AI compiler code of an AI compiler to a garbled circuit code by performing following procedures:
• sending a circuit graph of a garbled circuit corresponding to the garbled circuit code to a first electrical device through the transmission circuit, the garbled circuit having a plurality of logic gates;
• receiving a plurality of garbled truth tables for a plurality of candidate gates corresponding to each logic gate from the first electrical device through using OT protocol via the transmission circuit;
• and
• obtaining a target garbled truth table of each logic gate through using OT protocol based on the garbled truth tables for the candidate gates corresponding to each logic gate;
• wherein a plurality of key codebooks for the candidate gates corresponding to each logic gate are created by the first electrical device, an NN model is encrypted according to the key codebooks by the first electrical device, and the processor is further configured to generate a compiled NN model of an encrypted NN model according to the garbled circuit code with the target garbled truth table of each logic gate.

An electrical device for processing a neural network, comprising:

• a transmission circuit;
• a processor, configured to assist a server to transform an AI compiler code of an AI compiler to a garbled circuit code by performing following procedures:
• receiving a circuit graph of a garbled circuit corresponding to the garbled circuit code from the server through the transmission circuit, the garbled circuit having a plurality of logic gates;
• creating a plurality of key codebooks for a plurality of candidate gates corresponding to each logic gate;
• generating a plurality of garbled truth tables for the candidate gates corresponding to each logic gate;
• and
• transmitting the garbled truth tables for the candidate gates corresponding to each logic gate to the server through using OT protocol via the transmission circuit;
• wherein the processor is further configured to encrypt an NN model according to the key codebooks, a target garbled truth table of each logic gate is obtained through using OT protocol based on the garbled truth tables for the candidate gates corresponding to each logic gate by the server, and a compiled NN model of an encrypted NN model is generated according to the garbled circuit code with the target garbled truth table of each logic gate by the server.