Quasi-adiabatic logic circuits

A quasi-adiabatic logic gate comprising:

• first and second clock input terminals configured to receive complementary first and second periodic clock signals, respectively;
• one or more logic input terminals configured to receive one or more corresponding logic input signals;
• a logic output terminal configured to output a logic output signal;
• a pullup network including one or more pullup transistors configured to perform a pullup logic function, each of the one or more pullup transistors of the pullup network having a control node coupled to a corresponding one of the logic input terminals, the pullup network configured to modulate conductivity between a first supply node and an intermediate pullup node based on the pullup logic function that the pullup network is configured to perform and the logic input signals received on the logic input terminals;
• a pulldown network including one or more pulldown transistors configured to perform a pulldown logic function that is the complement of the pullup logic function performed by the pullup network, each of the one or more pulldown transistors of the pulldown network having a control node coupled to a corresponding one of the logic input terminals, the pulldown network configured to modulate conductivity between a second supply node and an intermediate pulldown node based on the pulldown logic function that the pulldown network is configured to perform and the logic input signals received on the logic input terminals;
• a pullup clocking transistor having a pullup control node coupled to the first clock terminal, the pullup clocking transistor having a control node coupled to the first clock input terminal, the pullup clocking transistor configured to modulate conductivity, based on the first periodic clock signal received on the first clock terminal, between the intermediate pullup node and a logic output terminal;
• a pulldown clocking transistor having a pulldown control node coupled to the second clock terminal, the pulldown clocking transistor having a control node coupled to the second clock input terminal, the pulldown clocking transistor configured to modulate conductivity, based on the second periodic clock signal received on the second clock terminal, between the intermediate pulldown node and a logic output terminal;
• wherein the first supply node is periodically driven by a first supply signal in a lagging phase relation with the second periodic clock signal, and wherein the second supply node is periodically driven by a second supply signal in a lagging phase relation with and the first clock signal.