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US 12,021,515 B2Granted
Semiconductor chip including chip pads of different surface areas, and semiconductor package including the semiconductor chip
AssigneeSK hynix Inc.
InventorsJu Il Eom, Woo Jin Lee, Hyung Ho Cho
Life of this patent
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Abstract
A semiconductor chip includes a chip body including a signal input/output circuit, a chip pad structure disposed on a surface of the chip body, the chip pad structure including first and second chip pads, the two chip pads having different surface areas, and a chip pad selection circuit disposed in the chip body and electrically connected to the signal input/output circuit and the chip pad structure. The chip pad selection circuit is configured to selectively and electrically connect one of the first and second chip pads to the signal input/output circuit.
Claims16
A semiconductor chip comprising:
- a chip body including a signal input/output circuit;
- a chip pad structure disposed on a surface of the chip body, the chip pad structure including an input/output pad unit and a control pad unit;
- and
- a chip pad selection circuit disposed in the chip body and electrically connected to the signal input/output circuit and the chip pad structure,
- wherein the input/output pad unit includes first and second chip pads, the first and second chip pads having different surface areas, and
- wherein the chip pad selection circuit is configured to select one of the first and second chip pads and configured to electrically connect the selected pad to the signal input/output circuit based on a control signal that is input from the control pad unit,
- wherein the chip body comprises:
- a chip substrate;
- a plurality of field effect transistors disposed in the chip substrate;
- an insulating structure disposed on the chip substrate and disposed between the plurality of field effect transistors and the chip pad structures;
- and
- a wiring structure disposed in the insulating structure,
- wherein the chip pad structure is electrically connected to the plurality of field effect transistors through the wiring structure,
- wherein the wiring structure comprises:
- a plurality of circuit layers disposed to be spaced apart from each other in a direction that is perpendicular to a surface of the chip substrate;
- a contact plug electrically connecting a lowermost layer of the plurality of circuit layers to the chip substrate;
- a contact via connecting the plurality of circuit layers to each other;
- and
- a redistribution line electrically connecting an uppermost layer of the plurality of circuit layers to the chip pad structure.
16 more elements
A semiconductor package comprising:
- a package substrate;
- and
- a semiconductor chip disposed on the package substrate,
- wherein the package substrate comprises:
- a substrate body;
- and
- a plurality of chip connection pads that are disposed on a surface of the substrate body,
- wherein the semiconductor chip comprises:
- a chip body;
- and
- a chip pad structure disposed on a surface of the chip body, the chip pad structure including a plurality of input/output pad units and at least one control pad unit,
- wherein the plurality of input/output pad units and the at least one control pad unit are disposed to respectively correspond to the plurality of chip connection pads,
- wherein each of the plurality of input/output pad units comprises first and second chip pads that are disposed to be spaced apart from each other, the first and second chip pads having different surface areas, and
- wherein one chip pad of the first and second chip pads is electrically connected to the corresponding chip connection pad among the plurality of chip connection pads,
- wherein the chip body comprises:
- a chip substrate;
- a plurality of field effect transistors disposed in the chip substrate;
- an insulating structure disposed on the chip substrate, the insulating structure disposed between the plurality of field effect transistors and the chip pad structure;
- and
- a wiring structure disposed in the insulating structure,
- wherein the chip pad structure is electrically connected to the plurality of field effect transistors through the wiring structure,
- wherein the wiring structure comprises:
- a plurality of circuit layers disposed to be spaced apart from each other in a direction that is perpendicular to a surface of the chip substrate;
- a contact plug electrically connecting a lowermost layer of the plurality of circuit layers to the chip substrate;
- a contact via connecting the plurality of circuit layers to each other;
- and a redistribution line electrically connecting an uppermost layer of the plurality of circuit layers to the chip pad structure.
23 more elements
Dependencies are inferred from the claim text.