Pre-amplification conditioning circuit for a transducer audio device

A microphone system comprising:

• a housing;
• a dynamic-type microphone configured within the housing and including a transducer operable to generate a differential microphone output signal at the microphone output based on a detected audio input signal;
• a pre-amplification conditioning circuit configured within the housing and comprising:
• a pair of matched junction field-effect transistors (JFETs) configured in a differential pair with common-source configuration and, when biased, operable to:
• receive the differential microphone output signal at corresponding gate electrodes of the matched JFETs;
• and
• generate an amplified microphone output signal at corresponding drain electrodes of the matched JFETs;
• a pair of bipolar junction transistors (BJTs) configured as a complimentary feedback transistor pair with each of the pair of BJTs coupled in parallel to a corresponding one of the pair of matched JFETs;
• a current sink coupled to corresponding source electrodes of the matched JFETs and corresponding emitter electrodes of the BJTs, the current sink operable to maintain a fixed total direct current through each of the matched JFETs and BJTs;
• and
• a phantom power generation circuit configured to generate either 24 V or 48 V of DC phantom power,
• wherein the pre-amplification conditioning circuit is DC biased via the phantom power generation circuit.

A microphone system comprising:

• a housing;
• a microphone configured within the housing;
• a pre-amplification conditioning circuit configured within the housing and comprising:
• a pair of matched junction field-effect transistors (JFETs) configured in a differential pair with common-source configuration and, when biased, operable to:
• receive a differential microphone output signal at corresponding gate electrodes of the matched JFETs;
• and
• generate an amplified microphone output signal at corresponding drain electrodes of the matched JFETs;
• and
• a pair of bipolar junction transistors (BJTs) configured as a complimentary feedback transistor pair with each of the pair of BJTs coupled in parallel to a corresponding one of the pair of matched JFETs,
• wherein for each of the BJTs:
• a collector electrode is coupled to a source electrode of the parallel-coupled corresponding JFET;
• a base electrode is coupled to the drain of the parallel-coupled corresponding JFET;
• and
• an emitter electrode is coupled to an output resistor that is series-coupled to the drain of the parallel-coupled corresponding WET.