Memory device for selectively operating multiple memory groups in different speeds and memory system including the same

Abstract

A memory device includes: a memory cell array; a sense amplifier for amplifying data stored in the memory cell array; a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier; a switch coupled to the first memory cell sub-array; and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the first memory cell sub-array has a first operation speed, and the second memory cell sub-array has a second operation speed slower than the first operation speed. When the switch is disabled, a bit line loading associated with the second memory cell sub-array is decreased, and the first memory cell sub-array has a third operation speed faster than the first operation speed.

Dependencies are inferred from the claim text.