Cache program operation of three-dimensional memory device with static random-access memory

A three-dimensional (3D) memory device, comprising:

• a first semiconductor structure comprising a 3D NAND memory array;
• a second semiconductor structure comprising peripheral circuits and an on-die static random-access memory (SRAM), the first semiconductor structure and the second semiconductor structure being bonded through a bonding interface to couple the 3D NAND memory array with the peripheral circuits and the on-die SRAM,
• wherein the peripheral circuits comprise:
• a page buffer coupled to the on-die SRAM;
• and
• a controller coupled to the on-die SRAM and the page buffer, and configured to:
• load a first batch of program data into the page buffer and cache the first batch of program data into the on-die SRAM, as a backup copy of the first batch of program data, together with a backup copy of a second batch of program data in the on-die SRAM;
• and
• in response to a status of programming the first batch of program data from the page buffer into the 3D NAND memory array being failed, transmit the backup copy of the first batch of program data in the on-die SRAM to the page buffer and program the backup copy of the first batch of program data in the page buffer into the 3D NAND memory array, wherein the controller is further configured to check the status of programming the first batch of program data and program a third batch of program data into the 3D NAND memory array simultaneously, the first batch of program data and the third batch of program data being generated consecutively.

A memory system, comprising:

• a host;
• a memory device coupled to the host and comprising;
• a three-dimensional (3D) NAND memory array;
• an on-die static random-access memory (SRAM);
• and
• peripheral circuits coupled to the 3D NAND memory array and formed on a same chip with the on-die SRAM, comprising:
• a page buffer coupled to the on-die SRAM and configured to sequentially receive a plurality of batches of program data from the host, the plurality of batches of program data being programmed into the 3D NAND memory array sequentially;
• and
• a controller coupled to the on-die SRAM and the page buffer, and configured to:
• load one batch of the plurality of batches of program data into the page buffer and cache the batch of program data into the on-die SRAM as a backup copy of the batch of program data;
• and
• in response to a status of programming the batch of program data from the page buffer into the 3D NAND memory array being failed, transmit the backup copy of the batch of program data in the on-die SRAM to the page buffer, and program the backup copy of the batch of program data in the page buffer into the 3D NAND memory array, wherein the controller is further configured to program an Mth batch of program data into the 3D NAND memory array, cache an (M+1)th batch of program data into the on-die SRAM, and check a status of programming an (M−1)th batch of program data simultaneously, M being an integer equal to or greater than 1.