US 12,019,563 B2Granted

Cache set permutations based on Galois Field operations

AssigneeIntel Corporation

InventorsScott Constable, Thomas Unterluggauer

Life of this patent

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Abstract

Systems, apparatuses and methods provide for technology that determines that first data associated with a first security domain is to be stored in a first permutated cache set, where the first permuted cache set is identified based on a permutation function that permutes at least one of a plurality of first cache indexes. The technology further determines that second data associated with a second security domain is to be stored in a second permutated cache set, where the second permuted cache set is identified based on the permutation function. The second permutated cache set may intersect the first permutated cache set at one data cache line to cause an eviction of first data associated with the first security domain from the one data cache line and bypass eviction of data associated with the first security domain from at least one other data cache line of the first permuted cache set.

Claims25

Dependent claims

A computing system comprising:

a processor to be associated with execution of a plurality of security domains including a first security domain and a second security domain;
and
a cache to store data associated with the execution of the plurality of security domains;
and
a memory including a set of executable program instructions, which when executed by the processor, cause the computing system to:
determine that first data associated with the first security domain is to be stored in a first permuted cache set associated with the cache, wherein the first permuted cache set is to be identified based on a permutation function that is to permute at least one of a plurality of first cache indexes;
and
determine that second data associated with the second security domain is to be stored in a second permuted cache set associated with the cache, wherein the second permuted cache set is to be identified based on the permutation function, and wherein the second permuted cache set intersects the first permuted cache set at one data cache line to cause an eviction of one data of the first data associated with the first security domain from the one data cache line and bypass eviction of at least one other data of the first data associated with the first security domain from at least one other data cache line of the first permuted cache set.

5 more elements

A semiconductor apparatus comprising:

one or more substrates;
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality logic hardware, the logic coupled to the one or more substrates to:
determine that first data associated with a first security domain of a plurality of security domains is to be stored in a first permuted cache set associated with a cache, wherein the first permuted cache set is to be identified based on a permutation function that is to permute at least one of a plurality of first cache indexes;
and
determine that second data associated with a second security domain of the plurality of security domains is to be stored in a second permuted cache set associated with the cache, wherein the second permuted cache set is to be identified based on the permutation function, and wherein the second permuted cache set intersects the first permuted cache set at one data cache line to cause an eviction of one data of the first data associated with the first security domain from the one data cache line and bypass eviction of at least one other data of the first data associated with the first security domain from at least one other data cache line of the first permuted cache set.

2 more elements

At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing device, cause the computing device to:

determine that first data associated with a first security domain of a plurality of security domains is to be stored in a first permuted cache set associated with a cache, wherein the first permuted cache set is to be identified based on a permutation function that is to permute at least one of a plurality of first cache indexes;
and
determine that second data associated with a second security domain is to be stored in a second permuted cache set associated with the cache, wherein the second permuted cache set is to be identified based on the permutation function, and wherein the second permuted cache set intersects the first permuted cache set at one data cache line to cause an eviction of one data of the first data associated with the first security domain from the one data cache line and bypass eviction of at least one other data of the first data associated with the first security domain from at least one other data cache line of the first permuted cache set.

Dependencies are inferred from the claim text.

Facts

Application: 17/032,883Filed 25 Sep 2020
Published: US 2021/0081332 A118 Mar 2021
Granted: 25 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 12/1433
The protection being physical, e.g. cell, word, block: for a module or a part of a module
G06F 12/1441
The protection being physical, e.g. cell, word, block: for a range
G06F 12/084
Multiuser, multiprocessor or multiprocessing cache systems: with a shared cache
G06F 12/0864
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…