FPGA-based real-time processing system and method applied to underwater acoustic positioning and realizing reconfigurability and multiple output

A field-programmable gate array (FPGA)-based real-time processing system applied to underwater acoustic positioning and realizing reconfigurablility and multiple output, the system comprising:

• a multi-interface control and command analysis module, for automatically completing sample information transmission and command analysis;
• a finite-state machine (FSM) of sample management, connected with the multi-interface control and command analysis module, for calculating related data, and completing splitting, flipping and writing of a sample;
• a parallel correlation processor group, connected with the FSM of sample management, for completing, in parallel, high-performance processing operations regarding a plurality of targets;
• a multi-output data former, connected with the parallel correlation processor group, for simultaneously realizing data formation of a multiple output result and outputting a flag bit signal to the outside to achieve universality, real-time performance and anti-noise performance of real-time correlation processing;
• and
• wherein multiple commands and data obtained by the multi-output data former are processed with “OR” as a logical relationship, and data acquisition is triggered when power is on (t=t0), and a flash memory (FLASH) is used to automatically read initialization commands and the data obtained;
• wherein commands comprise CMDFLASH the flash drive (t=t0), and when t>t0, serial port commands CMDUART, Ethernet commands CMDETH, commands CMDSPORT, other commands CMOTHER where the system commands are synthesized as follows;
• CMD
• SF3
• =
• {
• CMD
• FLASH
• ,
• τ
• =
• t
• 0
• CMD
• UART
• ⁢
• 
• CMD
• ETH
• 
• ⁢
• CMD
• SPORT
• 
• ⁢
• CMD
• OTHER
• ,
• τ
• >
• t
• 0
• wherein a calculation of a number of related points for expectation, a required number of parallel channels, and a paddle number of sub-correlation units is obtained with a maximum sampling frequency of analog to digital (AD) of fs, and a width of a signal to be detected is set to as Td, where the total number of related points for expectation is as follows:
• Ntotal=fsTd
• wherein a processing fast clock of the FPGA is fclk, the maximum number of relevant points for a single calculation is as follows:
• N
• max
• =
• f
• clk
• f
• s
• and the actual number of relevant points for a required number of parallel channels is as follows:
• N
• MUX
• ≥
• ⌈
• N
• total
• N
• max
• ⌉
• ,
• N
• MUX
• ≤
• N
• Ch
• -
• max
• and an effective number of correlation points in the single calculation of the sub-correlation unit is as follows:
• N
• valid
• =
• N
• total
• N
• MUX
• and an actual number of relevant points for a single calculation is as follows:
• Nd≤NMux, and
• where the paddle number of sub-correlation units is as follows:
• Npd=Nmux·Nd−Ntotal.