# US 12,016,253 B2 · Quantum chip test structure and fabrication method therefor, and test method and fabrication method for quantum chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,016,253 B2 - Document ID: US12016253B2 - Status: Granted - Kind: B2 - Application number: 18/315,378 - Filed: 2023-05-10 - Published: 2023-10-26 - Granted: 2024-06-18 - Earliest claimed: 2020-12-29 - Assignees: Origin Quantum Computing Technology (Hefei) Co., Ltd - Applicants: Origin Quantum Computing Technology (Hefei) Co., Ltd - Inventors: Yongjie Zhao - Web page: https://patentgrep.com/patent/US12016253B2 ## CPC - H10N 60/12: Josephson-effect devices - G01R 31/2644: {Adaptations of individual semiconductor devices to facilitate the testing thereof} - G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control - H10N 60/0156: {of devices comprising Nb or an alloy of Nb with one or more of the elements of group IVB, e.g. titanium, zirconium or hafnium} - H10N 60/0912: {of Josephson-effect devices} - H10N 60/20: Permanent superconducting devices - H10N 60/805: {for Josephson-effect devices} - H10N 60/85: Superconducting active materials - H10N 69/00: Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]} - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed are a quantum chip test structure and a fabrication method therefor, and a test method and a fabrication method for a quantum chip. The quantum chip test structure includes: a superconducting Josephson junction and a connection structure of the superconducting Josephson junction that are located on a substrate; a first isolation layer located on the connection structure, where a connection window penetrating through the first isolation layer is formed in the first isolation layer; a second isolation layer located on the first isolation layer, where a deposition window is formed in the second isolation layer; and an electrical connection portion located in the connection window and an electrical connection layer located in the deposition window, and the electrical connection layer is configured to implement electrical contact with a test device. ## Claims ### Claim 1 A quantum chip test structure, comprising: a superconducting Josephson junction and a connection structure of the superconducting Josephson junction that are located on a substrate; a first isolation layer located on the connection structure, wherein a connection window penetrating through the first isolation layer is formed in the first isolation layer; a second isolation layer located on the first isolation layer, wherein a deposition window is formed in the second isolation layer, the deposition window is configured to define a deposition region that is located on the first isolation layer, and the connection window is connected to the deposition window, the first isolation layer and the second isolation layer are made of at least one of a photoresist and an electron beam resist; and an electrical connection portion located in the connection window and an electrical connection layer located in the deposition window, wherein the electrical connection portion has one end connected to the connection structure and the other end connected to the electrical connection layer. ### Claim 2 (depends on 1) The quantum chip test structure according to claim 1, wherein an undercut structure is formed in the deposition window, and a thickness of the electrical connection layer is less than that of the second isolation layer. ### Claim 3 (depends on 1) The quantum chip test structure according to claim 1, wherein the connection structure is made of a superconducting material. ### Claim 4 (depends on 1) The quantum chip test structure according to claim 1, wherein the electrical connection layer and the electrical connection portion are made of Al. ### Claim 5 (depends on 1) The quantum chip test structure according to claim 1, wherein the superconducting Josephson junction is a structure formed by sandwiching an oxide film layer between two superconducting material layers. ### Claim 6 (depends on 5) The quantum chip test structure according to claim 5, wherein the connection structure is an electrical structure connected to the superconducting Josephson junction. ### Claim 7 (depends on 1) The quantum chip test structure according to claim 1, wherein the connection window is a through-hole formed in the first isolation layer, and one end of the through-hole extends to a surface of the connection structure. ### Claim 8 (depends on 1) A fabrication method for a quantum chip test structure according to claim 1, comprising: fabricating a superconducting Josephson junction and a connection structure of the superconducting Josephson junction on a substrate; forming a first isolation layer on the connection structure, and forming in the first isolation layer a connection window penetrating through the first isolation layer; forming a second isolation layer on the first isolation layer, and forming a deposition window in the second isolation layer, wherein the deposition window is configured to define a deposition region that is located on the first isolation layer, and the connection window is connected to the deposition window, the first isolation layer and the second isolation layer are made of at least one of a photoresist and an electron beam resist; and forming an electrical connection portion in the connection window and forming an electrical connection layer in the deposition window, wherein the electrical connection portion has one end connected to the connection structure and the other end connected to the electrical connection layer. ### Claim 9 (depends on 8) The fabrication method according to claim 8, wherein the formed deposition window has an undercut structure, and a thickness of the electrical connection layer is less than that of the second isolation layer. ### Claim 10 (depends on 8) The fabrication method according to claim 8, wherein before the step of forming an electrical connection portion in the connection window and forming an electrical connection layer in the deposition window, the fabrication method further comprises: removing an oxide film layer in a designated region of the connection structure, wherein the designated region is a region exposed by the connection window. ### Claim 11 (depends on 8) The fabrication method according to claim 8, wherein the fabricating a superconducting Josephson junction and a connection structure of the superconducting Josephson junction on a substrate comprises: forming a metal layer on the substrate; patterning the metal layer, so as to obtain the connection structure, a junction region and a ground region; sequentially forming a first electrode, an oxide film layer, and a second electrode on the substrate of the junction region, so that the first electrode being electrically connected to the connection structure and the second electrode being connected to the ground region; and obtaining the superconducting Josephson junction at an overlapping position of the first electrode, the oxide film layer, and the second electrode. ### Claim 12 (depends on 8) The fabrication method according to claim 8, wherein the forming an electrical connection portion in the connection window and forming an electrical connection layer in the deposition window comprises: forming, by means of a metal deposition process, a deposition material layer based on defining functions of the connection window and the deposition window, wherein the deposition material layer comprises the electrical connection portion in the connection window and the electrical connection layer in the deposition window. ### Claim 13 (depends on 1) A test method for a quantum chip, comprising: providing a quantum chip test structure disposed in a test device, wherein the quantum chip test structure is the quantum chip test structure according to claim 1; and performing an electrical test on a superconducting Josephson junction by directly contacting an electrical connection element of the test device with the electrical connection layer. ### Claim 14 (depends on 8) A test method for a quantum chip, comprising: providing a quantum chip test structure disposed in a test device, wherein the quantum chip test structure is obtained by using the fabrication method for a quantum chip test structure according to claim 8; and performing an electrical test on a superconducting Josephson junction by directly contacting an electrical connection element of the test device with an electrical connection layer. ### Claim 15 (depends on 13) A fabrication method for a quantum chip, comprising the test method for a quantum chip according to claim 13, wherein after testing is completed, the fabrication method comprises: peeling off and removing the first isolation layer and the second isolation layer, as well as the electrical connection layer and the electrical connection portion. ### Claim 16 (depends on 14) A fabrication method for a quantum chip, comprising the test method for a quantum chip according to claim 14, wherein after testing is completed, the fabrication method comprises: peeling off and removing a first isolation layer and a second isolation layer, as well as an electrical connection layer and an electrical connection portion.