# US 12,016,238 B2 · Display panel and method for manufacturing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,016,238 B2 - Document ID: US12016238B2 - Status: Granted - Kind: B2 - Application number: 17/286,464 - Filed: 2021-03-31 - Published: 2023-05-18 - Granted: 2024-06-18 - Earliest claimed: 2021-03-19 - Assignees: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Applicants: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Inventors: Wei Zou - Web page: https://patentgrep.com/patent/US12016238B2 ## CPC - H10K 59/8794: {Arrangements for heating and cooling} - H10K 59/1201: {Manufacture or treatment} - H10K 59/12: Active-matrix OLED [AMOLED] displays - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract The present invention discloses a display panel and a method for manufacturing the same. The display panel includes a thin film transistor array layer, a light-emitting device layer, and a thermal thin film layer. By means of connecting in series at least one thermistor in a light-emitting loop constituted by a driving transistor and a light-emitting device, the display panel can reduce or eliminate an influence of temperature on an attenuation of luminous brightness, and can meet the industry-recognized life evaluation standards. ## Claims ### Claim 1 A display panel, comprising: a substrate; a thin film transistor array layer on the substrate, the thin film transistor array layer comprising at least one driving transistor; a light-emitting device layer on the thin film transistor array layer, the light-emitting device layer having at least one light-emitting device and an anode layer; a thermal thin film layer disposed between the thin film transistor array layer and the light-emitting device layer and having at least one thermistor; and a planarization layer disposed between the thin film transistor array layer and the light-emitting device layer and on the thermal thin film layer, wherein a via hole is at least defined in the planarization layer, a first end of the via hole is connected to the thermal thin film layer, an another end of the via hole is connected to the anode layer, an orthographic projection of the anode layer on the substrate at least partially overlaps an orthographic projection of the via hole on the substrate, and an orthographic projection of the thermal thin film layer on the substrate at least partially overlaps an orthographic projection of the via hole on the substrate, wherein the at least one thermistor is connected in series in a light-emitting loop constituted by the driving transistor and the light-emitting device. ### Claim 2 (depends on 1) The display panel as claimed in claim 1, wherein the thermal thin film layer is disposed adjacent to the thin film transistor array layer. ### Claim 3 (depends on 1) The display panel as claimed in claim 1, wherein the driving transistor is connected to the thermistor. ### Claim 4 (depends on 3) The display panel as claimed in claim 3, wherein the anode layer comprises an anode; and a width of the anode is greater than or equal to a width of the thermistor. ### Claim 5 (depends on 1) The display panel as claimed in claim 1, wherein the thermal thin film layer is disposed between the planarization layer and the thin film transistor array layer. ### Claim 6 (depends on 1) The display panel as claimed in claim 1, wherein the thermistor at least partially covers the first end of the via hole or the second end of the via hole. ### Claim 7 A display panel, comprising: a substrate; a thin film transistor array layer on the substrate, the thin film transistor array layer comprising at least one driving transistor; a light-emitting device layer on the thin film transistor, the light-emitting device layer having at least one light-emitting device and an anode layer; and a thermal thin film layer having at least one thermistor, a planarization layer disposed between the thin film transistor array layer and the light-emitting device layer, wherein a via hole is at least defined in the planarization layer, an orthographic projection of the anode layer on the substrate at least partially overlaps an orthographic projection of the via hole on the substrate, and an orthographic projection of the thermal thin film layer on the substrate at least partially overlaps an orthographic projection of the via hole on the substrate, wherein the at least one thermistor is connected in series in a light-emitting loop constituted by the driving transistor and the light-emitting device. ### Claim 8 (depends on 7) The display panel as claimed in claim 7, wherein the thermal thin film layer is disposed adjacent to the thin film transistor array layer. ### Claim 9 (depends on 7) The display panel as claimed in claim 7, wherein a first end of the via hole is connected to a first end of the thermistor, a second end of the via hole is connected to the light-emitting device, and the driving transistor is connected to a second end of the thermistor. ### Claim 10 (depends on 9) The display panel as claimed in claim 9, wherein the anode layer comprises an anode; and a width of the anode is greater than or equal to a width of the thermistor. ### Claim 11 (depends on 7) The display panel as claimed in claim 7, wherein the thermal thin film layer is disposed between the planarization layer and the thin film transistor array layer. ### Claim 12 (depends on 7) The display panel as claimed in claim 7, wherein the thermistor at least partially covers the first end of the via hole or the second end of the via hole. ### Claim 13 (depends on 7) The display panel as claimed in claim 7, wherein the thermistor is connected in series between a source electrode of the driving transistor and an anode of the light-emitting device or between a drain electrode of the driving transistor and the anode of the light-emitting device. ### Claim 14 A method for manufacturing a display panel, comprising steps of: forming a substrate; forming a thin film transistor array layer on the substrate, wherein the thin film transistor array layer comprises at least one driving transistor; forming at least one thermal thin film layer, wherein the thermal thin film layer comprises at least one thermistor; forming a light-emitting device layer, wherein the light-emitting device layer comprises at least one light-emitting device and an anode layer; forming a planarization layer between the thin film transistor array layer and the light-emitting device layer and on the thermal thin film layer, wherein a via hole is at least defined in the planarization layer, a first end of the via hole is connected to the thermal thin film layer, an another end of the via hole is connected to the anode layer, an orthographic projection of the anode layer on the substrate at least partially overlaps an orthographic projection of the via hole on the substrate, and an orthographic projection of the thermal thin film layer on the substrate at least partially overlaps an orthographic projection of the via hole on the substrate; and connecting in series the at least one thermistor in a light-emitting loop constituted by the driving transistor and the light-emitting device.