# US 12,016,203 B2 · Display device including stressors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,016,203 B2 - Document ID: US12016203B2 - Status: Granted - Kind: B2 - Application number: 17/140,660 - Filed: 2021-01-04 - Published: 2021-10-28 - Granted: 2024-06-18 - Earliest claimed: 2020-04-22 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Junehwan Kim; Taeyoung Kim; Jongwoo Park; Kiju Im; Hyuncheol Hwang - Web page: https://patentgrep.com/patent/US12016203B2 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 2300/0426: Layout of electrodes and connections - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate} - H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon} - H10D 30/6731: {Top-gate only TFTs} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10D 30/6746: {Amorphous silicon} - H10D 30/751: {having composition variations in the channel regions} - H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions} - H10K 10/464: {Lateral top-gate IGFETs comprising only a single gate} - H10K 59/1213: {the pixel elements being TFTs} - H10K 59/35: comprising red-green-blue [RGB] subpixels - H10K 77/111: {Flexible substrates} - H10K 2102/311: {Flexible OLED} - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A display device having a thin-film transistor with increased mobility of electrons or holes includes a first semiconductor layer arranged on a substrate and including a first channel region, a first source region, and a first drain region; a first stressor arranged between the substrate and the first semiconductor layer and which overlaps the first source region in a plan view; a second stressor arranged between the substrate and the first semiconductor layer and which overlaps the first drain region in the plan view, where the second stressor is spaced apart from the first stressor; a gate insulating layer arranged on the first semiconductor layer; and a first gate electrode arranged on the gate insulating layer and which overlaps the first semiconductor layer in the plan view. ## Claims ### Claim 1 A display device comprising: a first semiconductor layer arranged on a substrate and including a first channel region, a first source region, and a first drain region; a first stressor arranged between the substrate and the first semiconductor layer and which is overlapped by the first source region in a thickness direction of the first semiconductor layer; a second stressor arranged between the substrate and the first semiconductor layer and which is overlapped by the first drain region in the thickness direction, the second stressor being spaced apart from the first stressor; a gate insulating layer arranged on the first semiconductor layer; a first gate electrode arranged on the gate insulating layer and which overlaps the first semiconductor layer in the thickness direction; and a second semiconductor layer arranged on a same layer as the first channel region of the first semiconductor layer is disposed on such that an entire lower surface of the second semiconductor layer and an entire lower surface of the first channel region directly contacts the same layer. ### Claim 2 (depends on 1) The display device of claim 1, further comprising a buffer layer arranged between the substrate and the first and second stressors and which defines a first groove and a second groove, respectively, wherein a portion of the first stressor is buried in the first groove, and a portion of the second stressor is buried in the second groove. ### Claim 3 (depends on 1) The display device of claim 1, further comprising a buffer layer arranged between the substrate and the first and second stressors and which defines a first through-hole and a second through-hole, respectively, both exposing a portion of the substrate, wherein a portion of the first stressor is buried in the first through-hole, and a portion of the second stressor is buried in the second through-hole. ### Claim 4 (depends on 1) The display device of claim 1, wherein a distance from a bottom surface of the substrate to a top surface of the first channel region in a thickness direction is less than a distance from the bottom surface of the substrate to a top surface of the first source region. ### Claim 5 (depends on 1) The display device of claim 1, wherein a first thin-film transistor includes the first semiconductor layer and the first gate electrode, wherein the first thin-film transistor is a switching thin-film transistor. ### Claim 6 (depends on 1) The display device of claim 1, wherein each of the first stressor and the second stressor has a compressive film stress. ### Claim 7 (depends on 1) The display device of claim 1, wherein a distance between particles of a material in the first stressor and a distance between particles of a material in the second stressor each are greater than a distance between particles of a material in the first semiconductor layer. ### Claim 8 A display device comprising: a first semiconductor layer arranged on a buffer layer and including a first channel region directly contacting the buffer layer, a first source region, and a first drain region; a first stressor arranged between the buffer layer and the first semiconductor layer and which is overlapped by the first source region in a thickness direction of the first semiconductor layer; a second stressor arranged between the buffer layer and the first semiconductor layer and which is overlapped by the first drain region in the thickness direction, the second stressor being spaced apart from the first stressor; a second semiconductor layer arranged directly on the buffer layer such that an entire lower surface of the second semiconductor layer contacts the buffer layer; a gate insulating layer arranged on the first semiconductor layer and the second semiconductor layer; a first gate electrode arranged on the gate insulating layer and which overlaps the first semiconductor layer in the thickness direction; and a second gate electrode arranged on the gate insulating layer and which overlaps the second semiconductor layer in the thickness direction.