# US 12,016,188 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,016,188 B2 - Document ID: US12016188B2 - Status: Granted - Kind: B2 - Application number: 17/840,213 - Filed: 2022-06-14 - Published: 2022-12-22 - Granted: 2024-06-18 - Earliest claimed: 2021-06-17 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hyuncheol Kim; Yongseok Kim; Dongsoo Woo; Kyunghwan Lee - Web page: https://patentgrep.com/patent/US12016188B2 ## CPC - G11C 13/0069: {Writing or programming circuits or methods} - G11C 13/0014: {comprising cells based on organic memory material} - G11C 13/003: {Cell access} - G11C 13/025: {using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes} - H10K 10/50: Bistable switching devices - H10K 19/10: comprising field-effect transistors - H10K 85/221: {Carbon nanotubes} - G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse} - G11C 2213/79: Array wherein the access device being a transistor - G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials - G11C: STATIC STORES (semiconductor memory devices H10B) - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes. ## Claims ### Claim 1 A semiconductor memory device comprising: a plurality of semiconductor patterns extending, above a substrate, in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas of the plurality of semiconductor patterns; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas of the plurality of semiconductor patterns; and a plurality of resistive switch units respectively connected to first sidewalls of the plurality of semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first electrode and the second electrode and including carbon nanotubes. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, further comprising a plurality of mold insulating layers, each being between two resistive switch units adjacent in the vertical direction among the plurality of resistive switch units, wherein the resistive switch material layer fills a switch material layer space between two adjacent mold insulating layers among the plurality of mold insulating layers. ### Claim 3 (depends on 2) The semiconductor memory device of claim 2, wherein the resistive switch material layer includes a carbon nanotube bundle filling the switch material layer space, the carbon nanotube bundle in the switch material layer space is configured to reversibly transit from a first arrangement state to a second arrangement state, the first arrangement state is a state in which carbon nanotubes in at least a portion of the carbon nanotube bundle are not in contact with each other, and the second arrangement state is a state in which the carbon nanotubes are in close contact with each other. ### Claim 4 (depends on 3) The semiconductor memory device of claim 3, wherein the resistive switch material layer in the first arrangement state has a first resistance, and the resistive switch material layer in the second arrangement state has a second resistance that is lower than the first resistance. ### Claim 5 (depends on 3) The semiconductor memory device of claim 3, wherein, based on a set voltage being applied to the plurality of resistive switch units, the carbon nanotube bundle is configured to transit from the first arrangement state to the second arrangement state, and based on a reset voltage being applied to the plurality of resistive switch units, the carbon nanotube bundle is configured to transit from the second arrangement state to the first arrangement state. ### Claim 6 (depends on 5) The semiconductor memory device of claim 5, wherein the set voltage is a negative voltage, the reset voltage is a positive voltage, and a magnitude of the reset voltage is the same as a magnitude of the set voltage. ### Claim 7 (depends on 1) The semiconductor memory device of claim 1, further comprising a plurality of bit lines connected to second sidewalls of the plurality of semiconductor patterns, extending in the vertical direction, and separated from each other in the second horizontal direction, wherein each of the plurality of word lines includes a first gate electrode and a second gate electrode respectively on a lower surface and an upper surface of a corresponding semiconductor pattern, and wherein the first gate electrode and the second gate electrode extend in the second horizontal direction. ### Claim 8 (depends on 7) The semiconductor memory device of claim 7, wherein the first gate electrode and the second gate electrode, each having a flat plate shape, are separated from each other. ### Claim 9 (depends on 7) The semiconductor memory device of claim 7, wherein each of the plurality of word lines further includes a connection part between the first gate electrode and the second gate electrode and on the sidewall of a corresponding semiconductor pattern, and each of the plurality of word lines covers the upper surface, the lower surface, and the sidewall of the corresponding semiconductor pattern. ### Claim 10 (depends on 1) The semiconductor memory device of claim 1, further comprising a plurality of bit lines connected to second sidewalls of the plurality of semiconductor patterns, extending in the second horizontal direction, and separated from each other in the vertical direction, wherein each of the plurality of word lines includes a first gate electrode and a second gate electrode respectively on a first side surface and a second side surface of a corresponding channel area, and wherein the first gate electrode and the second gate electrode extend in the vertical direction. ### Claim 11 A semiconductor memory device comprising: a plurality of semiconductor patterns extending, above a substrate, in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas of the plurality of semiconductor patterns; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas of the plurality of semiconductor patterns; and a plurality of resistive switch units respectively connected to first sidewalls of the plurality of semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first electrode and the second electrode, wherein the resistive switch material layer includes a carbon nanotube bundle and is configured to transit from a high resistance state to a low resistance state when a set voltage is applied to the plurality of resistive switch units. ### Claim 12 (depends on 11) The semiconductor memory device of claim 11, further comprising a plurality of mold insulating layers, each being between two resistive switch units adjacent in the vertical direction among the plurality of resistive switch units, wherein the resistive switch material layer fills a switch material layer space between two adjacent mold insulating layers among the plurality of mold insulating layers. ### Claim 13 (depends on 12) The semiconductor memory device of claim 12, wherein the carbon nanotube bundle in the switch material layer space is configured to reversibly transit from a first arrangement state to a second arrangement state, the first arrangement state is a state in which carbon nanotubes in at least a portion of the carbon nanotube bundle are not in contact with each other, and the second arrangement state is a state in which the carbon nanotubes are in close contact with each other. ### Claim 14 (depends on 13) The semiconductor memory device of claim 13, wherein, based on the set voltage being applied to the plurality of resistive switch units, the carbon nanotube bundle is configured to transit from the first arrangement state to the second arrangement state, and based on a reset voltage being applied to the plurality of resistive switch units, the carbon nanotube bundle is configured to transit from the second arrangement state to the first arrangement state. ### Claim 15 (depends on 14) The semiconductor memory device of claim 14, wherein the set voltage is a negative voltage, the reset voltage is a positive voltage, and a magnitude of the reset voltage is the same as a magnitude of the set voltage. ### Claim 16 (depends on 11) The semiconductor memory device of claim 11, further comprising a plurality of bit lines connected to second sidewalls of the plurality of semiconductor patterns, extending in the vertical direction, and separated from each other in the second horizontal direction, wherein each of the plurality of word lines includes a first gate electrode and a second gate electrode respectively on a lower surface and an upper surface of a corresponding semiconductor pattern, and wherein the first gate electrode and the second gate electrode extend in the second horizontal direction. ### Claim 17 A semiconductor memory device comprising: a plurality of semiconductor patterns extending, above a substrate, in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering lower surfaces and upper surfaces of the channel areas of the plurality of semiconductor patterns; a plurality of word lines on the lower surfaces and the upper surfaces of the channel areas of the plurality of semiconductor patterns, extending in the second horizontal direction, and extending in the vertical direction; a plurality of resistive switch units respectively connected to first sidewalls of the plurality of semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first electrode and the second electrode, the resistive switch material layer including a carbon nanotube bundle; and a plurality of bit lines connected to second sidewalls of the plurality of semiconductor patterns, extending in the vertical direction, and separated from each other in the second horizontal direction. ### Claim 18 (depends on 17) The semiconductor memory device of claim 17, further comprising a plurality of mold insulating layers, each being between two resistive switch units adjacent in the vertical direction among the plurality of resistive switch units, wherein the resistive switch material layer fills a switch material layer space between two adjacent mold insulating layers among the plurality of mold insulating layers. ### Claim 19 (depends on 18) The semiconductor memory device of claim 18, wherein the carbon nanotube bundle in the switch material layer space is configured to reversibly transit from a first arrangement state to a second arrangement state, the first arrangement state is a state in which carbon nanotubes in at least a portion of the carbon nanotube bundle are not in contact with each other, and the second arrangement state is a state in which the carbon nanotubes are in close contact with each other. ### Claim 20 (depends on 19) The semiconductor memory device of claim 19, wherein, based on a set voltage being applied to the plurality of resistive switch units, the carbon nanotube bundle is configured to transit from the first arrangement state to the second arrangement state, and based on a reset voltage being applied to the plurality of resistive switch units, the carbon nanotube bundle is configured to transit from the second arrangement state to the first arrangement state.