# US 12,016,184 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,016,184 B2 - Document ID: US12016184B2 - Status: Granted - Kind: B2 - Application number: 18/348,826 - Filed: 2023-07-07 - Published: 2023-11-02 - Granted: 2024-06-18 - Earliest claimed: 2018-03-20 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hidenobu Nagashima - Web page: https://patentgrep.com/patent/US12016184B2 ## CPC - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/40: characterised by the peripheral circuit region - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W 20/083: {the openings being via holes penetrating underlying conductors} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10P 50/283: {by chemical means} - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region. ## Claims ### Claim 1 A semiconductor memory device comprising: a stacked body provided above a substrate, in which conductive layers are isolated from each other and stacked along a first direction crossing a surface of the substrate; a source layer provided between the substrate and the stacked body; memory pillars passing through the stacked body along the first direction and being coupled to the source layer; a first insulation film provided above the stacked body, the first insulation film being located higher than upper surfaces of the memory pillars in the first direction; isolation portions passing through the stacked body and the first insulation film along the first direction, extending in a second direction crossing the first direction and isolating the stacked body in a third direction crossing the first direction and the second direction; a first member including silicon and nitrogen provided above the first insulation film; a second member including silicon and nitrogen provided on side walls of the isolation portions; four conductive members aligning along the third direction between two isolation portions adjacent in the third direction of the isolation portions and each penetrating the first insulation film and the stacked body along the first direction within a region between the two isolation portions; and lower interconnects provided between the substrate and the source layer, the four conductive members including a first conductor and a second conductor each functioning as a through contact electrically connected to a corresponding lower interconnect of the lower interconnects while being electrically insulated from the source layer, the first conductor and the second conductor being two conductive members of the four conductive members adjacent in the third direction and a portion of the stacked body within the region between the two isolation portions being provided between the first and second conductors. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein each of the memory pillars has a columnar shape extending in the first direction, each of the isolation portions has a plate shape extending in the first direction, and the second member is arranged between the memory pillars and a first isolation portion of the two isolation portions and between the memory pillars and a second isolation portion of the two isolation portions. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the first insulation film and the isolation portions include silicon oxide. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein intersections of the memory pillars and the conductive layers respectively function as memory cells. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein each of the memory pillars includes a charge storage film, a tunnel insulation film and a semiconductor layer. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, further comprising a contact provided on a first memory pillar of the memory pillars, the contact extending along the first direction in the first insulation film. ### Claim 7 (depends on 6) The semiconductor memory device according to claim 6, wherein an upper surface of the contact is located higher than upper surfaces of the four conductive members in the first direction. ### Claim 8 (depends on 6) The semiconductor memory device according to claim 6, wherein the contact is coupled to a bit line through a via provided on the contact. ### Claim 9 (depends on 6) The semiconductor memory device according to claim 6, wherein the contact includes tungsten. ### Claim 10 (depends on 1) The semiconductor memory device according to claim 1, further comprising a first via provided on the first conductor and a second via provided on the second conductor, the first and second vias penetrating the first member along the first direction. ### Claim 11 (depends on 10) The semiconductor memory device according to claim 10, wherein the first and second vias include tungsten. ### Claim 12 (depends on 1) The semiconductor memory device according to claim 1, wherein a contact or a via is provided on one of the memory pillars and one of the first and second conductors respectively, neither any contact nor any via being provided on both of the two isolation portions adjacent in the third direction. ### Claim 13 (depends on 12) The semiconductor memory device according to claim 12, wherein the contact or the via includes tungsten. ### Claim 14 (depends on 1) The semiconductor memory device according to claim 1, wherein the four conductive members include tungsten. ### Claim 15 (depends on 1) The semiconductor memory device according to claim 1, wherein the four conductive members are provided in four holes formed through the stacked body along the first direction respectively, a second insulation film being provided on a side wall of each of the four holes. ### Claim 16 (depends on 15) The semiconductor memory device according to claim 15, wherein the second insulation film is in contact with the portion of the stacked body and electrically insulates between the first and second conductors and the conductive layers in the stacked body. ### Claim 17 (depends on 15) The semiconductor memory device according to claim 15, wherein the second insulation film includes silicon oxide. ### Claim 18 (depends on 15) The semiconductor memory device according to claim 15, wherein lower ends of the four conductive members and the second insulation film terminate at a substantially same height. ### Claim 19 (depends on 1) The semiconductor memory device according to claim 1, wherein the four conductive members are provided in respective positions of the stacked body not isolated from each other. ### Claim 20 (depends on 1) The semiconductor memory device according to claim 1, further comprising a peripheral circuit provided below the lower interconnects, the first and second conductors being coupled to the peripheral circuit.