# US 12,016,183 B2 · Memory chip including control logic circuit with dynamic random-access memory and memory device including memory chips

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- Number: US 12,016,183 B2
- Document ID: US12016183B2
- Status: Granted
- Kind: B2
- Application number: 17/453,342
- Filed: 2021-11-02
- Published: 2023-03-30
- Granted: 2024-06-18
- Earliest claimed: 2021-09-29
- Assignees: Hon Hai Precision Industry Co., Ltd.
- Applicants: Hon Hai Precision Industry Co., Ltd.
- Inventors: Yan-Ru Chen
- Web page: https://patentgrep.com/patent/US12016183B2

## CPC

- H10B 43/40: characterised by the peripheral circuit region
- G06F 13/1657: {Access to multiple memories}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/00: Package configurations
- H10W 90/752: {between stacked chips}
- H10B: ELECTRONIC MEMORY DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory chip includes a memory cell circuit, a periphery circuit, an interconnect structure, and a control logic circuit. The periphery circuit is positioned under the memory cell circuit and electrically connected to the memory cell circuit. The interconnect structure is positioned on a side surface of the memory cell circuit. The control logic circuit is positioned under the interconnect structure. The control logic circuit is electrically connected to the interconnect structure and the periphery circuit and includes a dynamic random-access memory.

## Claims

### Claim 1

A memory chip, comprising:
a memory cell circuit;
a periphery circuit positioned under the memory cell circuit and electrically connected to the memory cell circuit;
an interconnect structure positioned on a side surface of the memory cell circuit; and
a control logic circuit positioned under the interconnect structure, wherein the control logic circuit is electrically connected to the interconnect structure and the periphery circuit, the control logic circuit comprises a dynamic random-access memory, a reduced instruction set computer core, a memory controller, and an error correction circuit, the reduced instruction set computer core is connected to the memory controller and the dynamic random-access memory, the memory controller is electrically connected to the peripheral circuit, and the error correction circuit is connected to the memory controller.

### Claim 2 (depends on 1)

The memory chip of claim 1, wherein the dynamic random-access memory comprises a capacitor array, the capacitor array comprises a plurality of capacitors, each capacitor comprises a conductive pillar, an insulating layer, and a conductive contact, the insulating layer covers a side surface and a lower surface of the conductive pillar, and the conductive contact is positioned under the insulating layer.

### Claim 3 (depends on 1)

The memory chip of claim 1, wherein the control logic circuit further comprises a read-only memory, and the read-only memory is connected to the reduced instruction set computer core.

### Claim 4 (depends on 1)

The memory chip of claim 1, wherein the peripheral circuit comprises a logic control, a register, a decoder, and an input and output control, the register is connected to the logic control and the input and output control, and the decoder is connected to the logic control and the input and output control.

### Claim 5 (depends on 4)

The memory chip of claim 4, further comprising a power management circuit, wherein the logic control is connected to the power management circuit.

### Claim 6 (depends on 1)

The memory chip of claim 1, wherein the memory cell circuit is a non-volatile memory cell circuit.

### Claim 7 (depends on 1)

A memory device, comprising:
at least two memory chips of claim 1, wherein the memory chips are stacked; and
at least one bonding wire, wherein the interconnect structures in the memory chips are electrically connected to each other by the at least one bonding wire.

### Claim 8

A memory chip, comprising:
a memory cell circuit;
a periphery circuit positioned under the memory cell circuit and electrically connected to the memory cell circuit;
an interconnect structure positioned on a side surface of the memory cell circuit; and
a control logic circuit positioned under the interconnect structure, wherein the control logic circuit is electrically connected to the interconnect structure and the periphery circuit, the control logic circuit comprises a dynamic random-access memory, a reduced instruction set computer core, a memory controller, an interface circuit, and a power management circuit, the reduced instruction set computer core is connected to the memory controller and the dynamic random-access memory, the memory controller is electrically connected to the peripheral circuit, and the interface circuit is connected to the power management circuit and the reduced instruction set computer core and is connected to the interconnect structure.