# US 12,016,181 B2 · 3D semiconductor device and structure with logic and memory

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- Number: US 12,016,181 B2
- Document ID: US12016181B2
- Status: Granted
- Kind: B2
- Application number: 17/665,560
- Filed: 2022-02-06
- Published: 2023-05-11
- Granted: 2024-06-18
- Earliest claimed: 2015-10-24
- Assignees: Monolithic 3D Inc.
- Applicants: Monolithic 3D Inc.
- Inventors: Zvi Or-Bach; Jin-Woo Han
- Web page: https://patentgrep.com/patent/US12016181B2

## CPC

- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 11/5621: {using charge storage in a floating gate}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 17/165: {Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002)}
- G11C 29/702: {by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones}
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/834: further characterised by the dopants
- H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor
- H10D 89/10: Integrated device layouts
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 2213/71: Three dimensional array
- H10B 41/10: characterised by the top-view layout
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A 3D device, the device including: a first level including logic circuits; a second level including a plurality of memory circuits, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the first level includes at least one voltage regulator circuit.

## Claims

### Claim 1

A 3D device, the device comprising:
a first level comprising logic circuits; and
a second level comprising a plurality of memory circuits,
wherein said first level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonds, and
wherein said first level comprises at least one voltage regulator circuit.

### Claim 2 (depends on 1)

The 3D device of claim 1,
wherein said second level comprises gate all around memory cells.

### Claim 3 (depends on 1)

The 3D device of claim 1,
wherein said device comprises redundancy circuits to replace at least one faulty logic circuit.

### Claim 4 (depends on 1)

The 3D device of claim 1,
wherein said device comprises redundancy circuits to replace at least one faulty memory circuit.

### Claim 5 (depends on 1)

The 3D device of claim 1, further comprising:
a first memory cell; and
a second memory cell,
wherein said second memory cell overlays said first memory cell, and
wherein said first memory cell is self-aligned to said second memory cell, being processed following a same lithography step.

### Claim 6 (depends on 1)

The 3D device of claim 1,
wherein said plurality of memory circuits comprise a multi-bit memory cell.

### Claim 7 (depends on 1)

The 3D device of claim 1,
wherein said first level comprises a plurality of decoder circuits.

### Claim 8

A 3D device, the device comprising:
a first level comprising logic circuits; and
a second level comprising a plurality of memory cells,
wherein said first level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonds, and
wherein said logic circuits comprise at least one power down control circuit.

### Claim 9 (depends on 8)

The 3D device of claim 8,
wherein said second level comprises gate all around memory cells.

### Claim 10 (depends on 8)

The 3D device of claim 8, further comprising:
a third level comprising a plurality of non-volatile memory cells,
wherein said third level overlays said second level, and
wherein said second level comprises a plurality of volatile memory cells.

### Claim 11 (depends on 8)

The 3D device of claim 8, further comprising:
a first memory cell; and
a second memory cell,
wherein said second memory cell overlays said first memory cell, and
wherein said first memory cell is self-aligned to said second memory cell, being processed following a same lithography step.

### Claim 12 (depends on 8)

The 3D device of claim 8, further comprising:
a third level comprising a plurality of memory cells, said third level overlaying said second level;
a fourth level overlaying said third level or underlying said first level,
wherein said fourth level comprises memory control circuits.

### Claim 13 (depends on 8)

The 3D device of claim 8,
wherein said first level comprises differential signaling circuits.

### Claim 14 (depends on 8)

The 3D device of claim 8,
wherein said second level comprises a thinned substrate, and
wherein said thinned substrate has a thickness less than 20 microns.

### Claim 15

A 3D device, the device comprising:
a first level comprising logic circuits; and
a second level comprising a plurality of memory circuits,
wherein said first level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonds, and
wherein said logic circuits comprise a plurality of antifuse structures.

### Claim 16 (depends on 15)

The 3D device of claim 15,
wherein said second level comprises gate all around memory cells.

### Claim 17 (depends on 15)

The 3D device of claim 15,
wherein said second level comprises at least one memory cell comprising a vertically oriented transistor channel.

### Claim 18 (depends on 15)

The 3D device of claim 15, further comprising:
a first memory cell; and
a second memory cell,
wherein said second memory cell overlays said first memory cell, and
wherein said first memory cell is self-aligned to said second memory cell, being processed following a same lithography step.

### Claim 19 (depends on 15)

The 3D device of claim 15,
wherein said plurality of memory circuits comprise at least four independently controlled memory arrays.

### Claim 20 (depends on 15)

The 3D device of claim 15,
wherein said device comprises redundancy circuits to replace a faulty circuit.