# US 12,016,178 B2 · Semiconductor device

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- Number: US 12,016,178 B2
- Document ID: US12016178B2
- Status: Granted
- Kind: B2
- Application number: 18/097,592
- Filed: 2023-01-17
- Published: 2023-06-08
- Granted: 2024-06-18
- Earliest claimed: 2020-05-28
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kyoung-Hee Kim; Woo Choel Noh; Ik Soo Kim; Jun Kwan Kim; Jinsub Kim; Yongjin Shin
- Web page: https://patentgrep.com/patent/US12016178B2

## CPC

- H10B 41/46: with an inter-gate dielectric layer also being used as part of the peripheral transistor
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10B 12/50: {Peripheral circuit region structures}
- H10B 41/10: characterised by the top-view layout
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/40: characterised by the peripheral circuit region
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including a cell array region and a peripheral circuit region;
a cell transistor on the cell array region of the substrate;
a peripheral transistor on the peripheral circuit region of the substrate;
a first interconnection layer connected to the cell transistor;
a second interconnection layer connected to the peripheral transistor;
a first interlayer dielectric layer covering the first interconnection layer; and
a second interlayer dielectric layer spaced apart from the first interconnection layer and covering the second interconnection layer,
wherein the second interlayer dielectric layer has a hydrogen concentration less than a hydrogen concentration of the first interlayer dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the second interlayer dielectric layer includes silicon oxide.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, wherein each of the first interconnection layer and the second interconnection layer has a lower width and an upper width on the lower width in a direction that is parallel to a top surface of the substrate, the upper width being less than the lower width.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a data storage structure connected to the first interconnection layer.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a passivation layer on the first interlayer dielectric layer and the second interlayer dielectric layer.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, wherein a top surface of the second interlayer dielectric layer is coplanar with a top surface of the first interlayer dielectric layer.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, wherein a material of the first interlayer dielectric layer is different from a material of the second interlayer dielectric layer.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a first antireflective layer on the first interconnection layer; and
a second antireflective layer on the second interconnection layer.

### Claim 9 (depends on 8)

The semiconductor device as claimed in claim 8, wherein the second interlayer dielectric layer covers a top surface of the second antireflective layer.

### Claim 10

A semiconductor device, comprising:
a substrate including a cell array region and a peripheral circuit region;
a cell transistor on the cell array region of the substrate;
a peripheral transistor on the peripheral circuit region of the substrate;
a first interconnection layer connected to the cell transistor;
a second interconnection layer connected to the peripheral transistor;
a first interlayer dielectric layer covering the first interconnection layer; and
a second interlayer dielectric layer spaced apart from the first interconnection layer and covering the second interconnection layer,
wherein a top surface of the first interlayer dielectric layer is coplanar with a top surface of the second interlayer dielectric layer, and
wherein a material of the first interlayer dielectric layer is different from a material of the second interlayer dielectric layer.

### Claim 11 (depends on 10)

The semiconductor device as claimed in claim 10, further comprising an interface layer between the substrate and the first interconnection layer and the second interconnection layer.

### Claim 12 (depends on 10)

The semiconductor device as claimed in claim 10, further comprising:
a first antireflective layer on the first interconnection layer; and
a second antireflective layer on the second interconnection layer.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12, wherein the second interlayer dielectric layer covers a sidewall of the second interconnection layer and a top surface of the second antireflective layer.

### Claim 14 (depends on 10)

The semiconductor device as claimed in claim 10, wherein each of the first interconnection layer and the second interconnection layer has a lower width and an upper width on the lower width in a direction that is parallel to a top surface of the substrate, the upper width being less than the lower width.

### Claim 15 (depends on 10)

The semiconductor device as claimed in claim 10, wherein the second interlayer dielectric layer includes silicon oxide.

### Claim 16

A semiconductor device, comprising:
a substrate including a cell array region and a peripheral circuit region;
a plurality of cell transistors on the cell array region of the substrate;
a plurality of capacitors on the plurality of cell transistors, each of the plurality of capacitors connected to a corresponding one of the plurality of cell transistors;
a plurality of peripheral transistors on the peripheral circuit region of the substrate;
a first lower interconnection layer connected to one of the plurality of capacitors;
a second lower interconnection layer connected to one of the plurality of peripheral transistors;
an interface layer covering the first lower interconnection layer and the second lower interconnection layer;
a first upper interconnection layer connected to the first lower interconnection layer;
a second upper interconnection layer connected to the second lower interconnection layer;
a first interlayer dielectric layer covering the first upper interconnection layer;
a second interlayer dielectric layer spaced apart from the first upper interconnection layer and covering the second upper interconnection layer; and
a passivation layer on the first interlayer dielectric layer and the second interlayer dielectric layer,
wherein the semiconductor device includes:
a plurality of first impurity regions and a plurality of second impurity regions in an upper portion of an active section defined by a device isolation layer;
a plurality of bit-line contacts connected to the plurality of first impurity regions; and
a plurality of node contacts connected to the plurality of second impurity regions, and
wherein each of the plurality of capacitors includes a bottom electrode, a top electrode, and a dielectric layer between the bottom electrode and the top electrode.

### Claim 17 (depends on 16)

The semiconductor device as claimed in claim 16, wherein the first lower interconnection layer or the second lower interconnection layer includes a barrier layer.

### Claim 18 (depends on 16)

The semiconductor device as claimed in claim 16, wherein a material of the first interlayer dielectric layer is different from a material of the second interlayer dielectric layer.

### Claim 19 (depends on 16)

The semiconductor device as claimed in claim 16, wherein the second interlayer dielectric layer has a hydrogen concentration less than a hydrogen concentration of the first interlayer dielectric layer.

### Claim 20 (depends on 16)

The semiconductor device as claimed in claim 16, wherein a top surface of the second interlayer dielectric layer is coplanar with a top surface of the first interlayer dielectric layer.