# US 12,016,176 B2 · Semiconductor memory device and method for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,016,176 B2 - Document ID: US12016176B2 - Status: Granted - Kind: B2 - Application number: 17/368,130 - Filed: 2021-07-06 - Published: 2022-06-16 - Granted: 2024-06-18 - Earliest claimed: 2020-12-11 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hyeon-Woo Jang; Soo Ho Shin - Web page: https://patentgrep.com/patent/US12016176B2 ## CPC - H10B 12/50: {Peripheral circuit region structures} - H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug} - H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells} - H10B 12/315: {with the capacitor higher than a bit line} - H10B 12/34: {the transistor being at least partially in a trench in the substrate} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device comprises a substrate which includes a cell region, and a peri region defined around the cell region, the cell region including an active region defined by an element separation film, a storage pad connected to the active region of the cell region, a peri gate structure placed on the substrate of the peri region, a peri contact plug placed on both sides of the peri gate structure and connected to the substrate, a first interlayer insulating film which is placed on the storage pad and the pen contact plug, and includes a nitride-based insulating material, and an information storage unit connected to the storage pad, wherein a thickness of the first interlayer insulating film on an upper surface of the storage pad is smaller than a thickness of the first interlayer insulating film on an upper surface of the peri contact plug. ## Claims ### Claim 1 A semiconductor memory device, comprising: a substrate including a cell region and a peri region around the cell region, the cell region including an active region defined by an element separation film; a storage pad connected to the active region of the cell region; a peri gate structure on the substrate of the peri region; a peri contact plug on both sides of the peri gate structure and electrically connectable to the substrate; a first interlayer insulating film on the storage pad and on the peri contact plug, and including a nitride-based insulating material; and an information storage circuit connected to the storage pad, wherein a thickness of the first interlayer insulating film on an upper surface of the storage pad is less than a thickness of the first interlayer insulating film on an upper surface of the peri contact plug, wherein the first interlayer insulating film is on and over the upper surface of the peri contact plug, and wherein the first interlayer insulating film includes a lower interlayer insulating film, the lower interlayer insulating is on and over the upper surface of the peri contact plug and is not on the upper surface of the storage pad. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the first interlayer insulating film further includes an upper interlayer insulating film on the lower interlayer insulating film. ### Claim 3 (depends on 2) The semiconductor memory device of claim 2, wherein the upper interlayer insulating film is on the upper surface of the storage pad and the upper surface of the peri contact plug. ### Claim 4 (depends on 1) The semiconductor memory device of claim 1, wherein the information storage circuit includes a lower electrode connected to the storage pad, a capacitor dielectric film on the lower electrode, and a plate upper electrode on the capacitor dielectric film. ### Claim 5 (depends on 4) The semiconductor memory device of claim 4, further comprising: a second interlayer insulating film placed on the first interlayer insulating film and covering side walls of the plate upper electrode, wherein the second interlayer insulating film directly contacts the first interlayer insulating film. ### Claim 6 (depends on 4) The semiconductor memory device of claim 4, further comprising: a second interlayer insulating film on the first interlayer insulating film and covering side walls of the plate upper electrode, wherein the capacitor dielectric film extends along a boundary between the first interlayer insulating film and the second interlayer insulating film. ### Claim 7 (depends on 4) The semiconductor memory device of claim 4, wherein the first interlayer insulating film includes a lower interlayer insulating film, and an upper interlayer insulating film on the lower interlayer insulating film, and the lower interlayer insulating film includes a first portion vertically overlapping the plate upper electrode, and a second portion which does not vertically overlap the plate upper electrode. ### Claim 8 (depends on 7) The semiconductor memory device of claim 7, wherein a thickness of a first portion of the lower interlayer insulating film is greater than a thickness of a second portion of the lower interlayer insulating film. ### Claim 9 (depends on 1) The semiconductor memory device of claim 1, wherein an upper surface of a peri wiring line is on a same plane as the upper surface of the storage pad. ### Claim 10 A semiconductor memory device, comprising: a substrate including a cell region and a peri region around the cell region, the cell region including an active region defined by an element separation film; a cell separation film defining the cell region in the substrate; a storage pad connected to the active region of the cell region; a peri gate structure on the substrate of the peri region; a peri contact plug on both sides of the peri gate structure and electrically connectable to the substrate, an upper surface of a peri wiring line on a same plane as an upper surface of the storage pad; a first interlayer insulating film on the storage pad and on the peri contact plug and including a nitride-based insulating material; and a capacitor including a lower electrode connected to the storage pad, a capacitor dielectric film on the lower electrode, and a plate upper electrode on the capacitor dielectric film, wherein an upper surface of the first interlayer insulating film includes a step structure on the cell separation film, wherein the first interlayer insulating film is on and over thein upper surface of the peri contact plug, and wherein a lower interlayer insulating film is on the upper surface of the peri contact plug and is not on the upper surface of the storage pad. ### Claim 11 (depends on 10) The semiconductor memory device of claim 10, wherein a thickness of the first interlayer insulating film on the upper surface of the peri contact plug is greater than a thickness of the first interlayer insulating film on the upper surface of the storage pad. ### Claim 12 (depends on 10) The semiconductor memory device of claim 10, wherein the first interlayer insulating film includes tithe lower interlayer insulating film, and an upper interlayer insulating film on the lower interlayer insulating film, the lower interlayer insulating film includes a termination on the cell separation film, and the step structure is defined by the termination of the lower interlayer insulating film. ### Claim 13 (depends on 12) The semiconductor memory device of claim 12, wherein the lower interlayer insulating film includes a plurality of insulating films sequentially stacked on the substrate. ### Claim 14 (depends on 10) The semiconductor memory device of claim 10, wherein the step structure is at a position that vertically overlaps the plate upper electrode. ### Claim 15 (depends on 10) The semiconductor memory device of claim 10, further comprising: a second interlayer insulating film on the first interlayer insulating film and covering side walls of the plate upper electrode, wherein the second interlayer insulating film directly contacts the first interlayer insulating film. ### Claim 16 A semiconductor memory device, comprising: a substrate including a cell region, and a peri region around the cell region, the cell region including an active region defined by an element separation film; a cell separation film defining the cell region of the substrate; a bit line structure including a cell conductive line and a cell line capping film on the cell conductive line, the bit line structure on the substrate of the cell region; a cell gate electrode placed inside the substrate of the cell region and intersecting the cell conductive line; a storage pad on a side surface of the bit line structure and connected to the active region of the cell region; a peri gate structure on the substrate of the peri region; a peri contact plug on both sides of the peri gate structure and electrically connectable to the substrate; a capacitor including a lower electrode connected to the storage pad, a capacitor dielectric film on the lower electrode, and a plate upper electrode on the capacitor dielectric film; a lower interlayer insulating film on the peri contact plug and including a nitride-based insulating material, a termination of the lower interlayer insulating film covered by the plate upper electrode; and an additional interlayer insulating film on the lower interlayer insulating film and covering side walls of the plate upper electrode, wherein the lower interlayer insulating film is not on an upper surface of the storage pad. ### Claim 17 (depends on 16) The semiconductor memory device of claim 16, further comprising: an etching stop film on the upper surface of the storage pad, wherein the etching stop film extends between the lower interlayer insulating film and the plate upper electrode. ### Claim 18 (depends on 17) The semiconductor memory device of claim 17, wherein the etching stop film extends between the lower interlayer insulating film and the additional interlayer insulating film. ### Claim 19 (depends on 16) The semiconductor memory device of claim 16, wherein the capacitor dielectric film is not between the lower interlayer insulating film and the additional interlayer insulating film.