# US 12,016,175 B2 · Semiconductor device

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- Number: US 12,016,175 B2
- Document ID: US12016175B2
- Status: Granted
- Kind: B2
- Application number: 18/226,891
- Filed: 2023-07-27
- Published: 2023-11-16
- Granted: 2024-06-18
- Earliest claimed: 2020-12-01
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Eun Young Lee; Do Hyung Kim; Taek Jung Kim; Seung Jong Park; Jae Wha Park; Youn Jae Cho
- Web page: https://patentgrep.com/patent/US12016175B2

## CPC

- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate including an element isolation film and an active region defined by the element isolation film; a word line crossing the active region in a first direction; and a bit line structure on the substrate and connected to the active region, the bit line structure extending in a second direction crossing the first direction, wherein the bit line structure includes a first cell interconnection film including an amorphous material or ruthenium, a second cell interconnection film on and extending along the first cell interconnection film and including ruthenium, and a cell capping film on and extending along the second cell interconnection film.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including an element isolation film and an active region defined by the element isolation film;
a word line crossing the active region of the substrate in a first direction that is parallel to a top surface of the substrate; and
a bit line structure crossing the active region of the substrate in a second direction that crosses the first direction,
wherein:
the bit line structure includes:
a first conductive pattern on the active region of the substrate,
a second conductive pattern on the first conductive pattern,
a third conductive pattern on the second conductive pattern,
a fourth conductive pattern on the third conductive pattern, and
a capping pattern on the fourth conductive pattern,
the first conductive pattern of the bit line structure includes a doped semiconductor material,
the second conductive pattern of the bit line structure includes a metal silicide,
the third conductive pattern of the bit line structure includes a barrier film, and
the fourth conductive pattern of the bit line structure includes molybdenum (Mo).

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first conductive pattern of the bit line structure includes silicon (Si).

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the second conductive pattern of the bit line structure includes titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, ruthenium (Ru) silicide, or tungsten (W) silicide.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the third conductive pattern of the bit line structure includes a metal-containing material or graphene.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the third conductive pattern of the bit line structure includes tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tungsten silicon nitride (WSiN), or graphene.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the word line includes a gate electrode that is fully buried in the substrate.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a bit line contact on the active region of the substrate,
wherein an upper surface of the bit line contact is substantially coplanar with an upper surface of the first conductive pattern of the bit line structure.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a storage contact on the element isolation film and the active region of the substrate and adjacent to at least one side of the bit line structure;
a landing pad on the storage contact; and
a capacitor structure on the landing pad.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the capping pattern of the bit line structure includes silicon nitride, silicon oxynitride, or silicon oxide.

### Claim 10 (depends on 7)

The semiconductor device as claimed in claim 7, wherein the bit line contact includes a doped semiconductor material.

### Claim 11 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising an insulation film between the element isolation film of the substrate and the first conductive pattern of the bit line structure,
wherein the insulation film includes an oxide film and a nitride film.

### Claim 12 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the second conductive pattern of the bit line structure includes titanium (Ti) silicide.

### Claim 13 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the third conductive pattern of the bit line structure includes titanium silicon nitride (TiSiN) and tungsten silicon nitride (WSiN).

### Claim 14 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
the bit line structure includes a bit line spacer that is on a side surface of each of the first to fourth conductive patterns of the bit line structure, and
the bit line spacer of the bit line structure includes a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbonitride film (SiOCN), air, or a combination thereof.

### Claim 15 (depends on 11)

The semiconductor device as claimed in claim 11, wherein:
the bit line structure includes a bit line spacer that is on a side surface of each of the first to fourth conductive patterns of the bit line structure, and
a bottom surface of the bit line spacer of the bit line structure is in contact with a top surface of the insulation film.

### Claim 16

A semiconductor device, comprising:
a substrate including an active region;
a gate electrode fully buried in the substrate;
a bit line structure on the substrate;
a bit line contact arranged between the substrate and the bit line structure and electrically connected to the active region of the substrate;
a storage contact arranged adjacent to the bit line structure and electrically connected to the active region of the substrate;
a landing pad on the storage contact; and
a capacitor structure on the landing pad,
wherein:
the bit line structure includes:
a first conductive pattern on the active region of the substrate,
a second conductive pattern on the first conductive pattern, and
a capping pattern on the second conductive pattern,
the first conductive pattern of the bit line structure includes titanium nitride (TiN),
the second conductive pattern of the bit line structure includes molybdenum (Mo), and
the capping pattern of the bit line structure includes silicon nitride, silicon oxynitride, or silicon oxide.

### Claim 17 (depends on 16)

The semiconductor device as claimed in claim 16, wherein:
the bit line structure includes a third conductive pattern between the substrate and the first conductive pattern of the bit line structure, and
the third conductive pattern of the bit line structure includes titanium (Ti) silicide.

### Claim 18 (depends on 17)

The semiconductor device as claimed in claim 17, wherein:
the bit line structure includes a fourth conductive pattern between the substrate and the third conductive pattern of the bit line structure, and
the fourth conductive pattern of the bit line structure includes a doped semiconductor material.

### Claim 19 (depends on 16)

The semiconductor device as claimed in claim 16, wherein the bit line contact includes a doped semiconductor material.

### Claim 20

A semiconductor device, comprising:
a substrate including an active region;
a gate electrode fully buried in the substrate;
a bit line structure on the substrate;
a bit line contact arranged between the substrate and the bit line structure and electrically connected to the active region of the substrate;
a storage contact arranged adjacent to the bit line structure and electrically connected to the active region of the substrate;
a landing pad on the storage contact; and
a capacitor structure on the landing pad,
wherein:
the bit line structure includes:
a first conductive pattern on the active region of the substrate,
a second conductive pattern on the first conductive pattern, and
a capping pattern on the second conductive pattern,
the first conductive pattern of the bit line structure includes tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tungsten silicon nitride (WSiN), or graphene, and
the second conductive pattern of the bit line structure includes molybdenum (Mo).