# US 12,016,174 B2 · Semiconductor device and method for forming the same

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- Number: US 12,016,174 B2
- Document ID: US12016174B2
- Status: Granted
- Kind: B2
- Application number: 17/673,804
- Filed: 2022-02-17
- Published: 2023-03-09
- Granted: 2024-06-18
- Earliest claimed: 2021-09-09
- Assignees: Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicants: Fujian Jinhua Integrated Circuit Co., Ltd.
- Inventors: Min-Teng Chen
- Web page: https://patentgrep.com/patent/US12016174B2

## CPC

- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/482: {Bit lines}
- H10D 1/716: {having vertical extensions}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate, a plurality of bit lines, a plurality of contacts, a plurality of storage node pads, a capacitor structure and a plurality of first interface layers. The bit lines and the contacts are disposed on the substrate, and the contacts are alternately and separately disposed with the bit lines. The storage node pads are disposed on the contacts and the bit lines, and are respectively aligned with the contacts. The capacitor structure is disposed on the storage node pads. The first interface layers are disposed between the storage node pads and the capacitor structure, and the first interface layers include a metal nitride material. The first interface layers may improve the granular size of the storage node pads, and reduce the surface roughness thereof, and further improve the electrical connection between the storage nodes and transistor components below.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a plurality of bit lines, disposed on the substrate;
a plurality of contacts, disposed on the substrate, and alternatively and separately disposed with the bit lines;
a plurality of storage node pads, disposed on the contacts and the bit lines;
a plurality of capacitors, disposed on the storage node pads, wherein each of the capacitors comprises a bottom electrode layer, a capacitor dielectric layer and a top electrode layer; and
an interface layer, disposed above each of the storage node pads and surrounding at least a portion of the bottom electrode layer of each of the capacitors, wherein the capacitor dielectric layer contacts a top surface of the interface layer and a top surface of the bottom electrode layer of each of the capacitors.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the bottom electrode layer is provided with a pillar structure.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the interface layer comprises a material consisted of metal oxide.

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein the bottom electrode layer is provided with a composite layer structure, the interface layer is disposed within the composite layer structure.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the composite layer structure comprises a first conductive layer and a second conductive layer sequentially stacked, the interface layer is disposed between the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer comprise the same materials.

### Claim 6

A method for forming a semiconductor device, comprising:
providing a substrate;
forming a plurality of bit lines on the substrate;
forming a plurality of contacts on the substrate, and the bit lines and the contacts are arranged alternatively with each other;
forming a plurality of storage node pads on the contacts and the bit lines;
forming a capacitor structure on the storage node pads, wherein forming the capacitor structure comprise:
forming a support layer structure on the substrate, and the support layer structure comprises at least one oxide layer and at least one nitride layer alternatively stacked;
forming a plurality of openings in the support layer structure, each of the openings exposes one of the storage node pads;
forming a plurality of bottom electrode layers in the openings; and
removing the at least one oxide layer in the support layer structure; and
performing a first surface treatment on the storage node pads to form the first interface layers, between the storage node pads and the capacitor structure, and the first interface layers comprise a material consisted of metal nitride.

### Claim 7 (depends on 6)

The method for forming the semiconductor device of claim 6, wherein the first surface treatment comprises a nitrogen treatment.

### Claim 8 (depends on 6)

The method for forming the semiconductor device of claim 6, further comprising:
after the bottom electrode layers are formed, a capacitor dielectric layer and a top electrode layer are sequentially formed on the bottom electrode layers.

### Claim 9 (depends on 6)

The method for forming the semiconductor device of claim 6, further comprising:
performing a second surface treatment in the openings to form a second interface layer, the second interface layer comprises a material different from the material of the first interface layers.

### Claim 10 (depends on 9)

The method for forming the semiconductor device of claim 9,
wherein the second surface treatment is an ex-situ treatment.

### Claim 11 (depends on 6)

The method for forming the semiconductor device of claim 6, wherein the formation of the bottom electrode layers further comprising:
forming a first conductive layer on the surface of the openings conformally;
performing a third surface treatment on the first conductive layer to form a third interface layer, the third interface layer comprises a material different from the material of the first interface layers; and
forming a second conductive layer on the third interface layer, wherein the first conductive layer and the second conductive layer comprise the same materials.

### Claim 12 (depends on 11)

The method for forming the semiconductor device of claim 11,
wherein the third surface treatment is an ex-situ treatment.

### Claim 13 (depends on 11)

The method for forming the semiconductor device of claim 11,
wherein the second conductive layer fills up the openings.

### Claim 14 (depends on 11)

The method for forming the semiconductor device of claim 11,
wherein the third surface treatment is performed under vacuum relief to introduce oxygen for reaction.