# US 12,016,173 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 12,016,173 B2
- Document ID: US12016173B2
- Status: Granted
- Kind: B2
- Application number: 17/388,033
- Filed: 2021-07-29
- Published: 2022-03-03
- Granted: 2024-06-18
- Earliest claimed: 2020-08-27
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Te-Hsuan Peng; Kai Jen
- Web page: https://patentgrep.com/patent/US12016173B2

## CPC

- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)}
- H10D 1/716: {having vertical extensions}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10P 95/062: {involving a dielectric removal step}
- H10P 95/066: {the removal being a selective chemical etching step, e.g. selective dry etching through a mask}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including a substrate, a capacitor, a stop layer, a first contact, and a second contact is provided. The substrate includes a memory array region and a peripheral circuit region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. The stop layer is located on the second electrode in the memory array region and extends into the peripheral circuit region. A material of the stop layer is not a conductive material. The first contact is located in the memory array region, passes through the stop layer, and is electrically connected to the second electrode. The second contact is located in the peripheral circuit region and passes through the stop layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate comprising a memory array region and a peripheral circuit region;
a capacitor located in the memory array region and comprising:
a first electrode located on the substrate;
a second electrode located on the first electrode; and
an insulating layer located between the first electrode and the second electrode;
a stop layer comprising a first portion located on the second electrode in the memory array region and a second portion located in the peripheral circuit region, wherein the first portion extends to the second portion, a material of the stop layer is not a conductive material, and a top surface of the first portion is higher than a top surface of the second portion;
a first contact located in the memory array region, passing through the stop layer, and electrically connected to the second electrode; and
a second contact located in the peripheral circuit region and passing through the stop layer, wherein
the second electrode comprises a multilayer structure, and
the second electrode comprises:
a first conductive layer, wherein a material of the first conductive layer comprises a doped semiconductor material; and
a second conductive layer located between the first conductive layer and the insulating layer, wherein a material of the second conductive layer comprises titanium, titanium nitride, or a combination thereof.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the stop layer extends along a sidewall of the capacitor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a buffer layer located in the memory array region and the peripheral circuit region and located between the stop layer and the second electrode, wherein a material of the buffer layer comprises oxide, and a material of the stop layer comprises nitride.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a planarization layer located on the stop layer, wherein a material of the planarization layer comprises oxide, and a material of the stop layer comprises nitride.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, further comprising:
a dielectric layer located on the planarization layer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a first barrier layer located between the first contact and the second electrode; and
a second barrier layer located between the second contact and the substrate.

### Claim 7

A semiconductor device, comprising:
a substrate comprising a memory array region and a peripheral circuit region;
a capacitor located in the memory array region and comprising:
a first electrode located on the substrate;
a second electrode located on the first electrode; and
an insulating layer located between the first electrode and the second electrode;
a stop layer comprising a first portion located on the second electrode in the memory array region and a second portion located in the peripheral circuit region, wherein the first portion extends to the second portion, a material of the stop layer is not a conductive material, and a top surface of the first portion is higher than a top surface of the second portion;
a first contact located in the memory array region, passing through the stop layer, and electrically connected to the second electrode;
a second contact located in the peripheral circuit region and passing through the stop layer;
a buffer layer located in the memory array region and the peripheral circuit region and located between the stop layer and the second electrode; and
a planarization layer located on the stop layer, wherein
a material of the stop layer is different from a material of the buffer layer and a material of the planarization layer.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the material of the stop layer comprises nitride, the material of the buffer layer comprises oxide, and the material of the planarization layer comprises oxide.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein the stop layer extends along a sidewall of the capacitor.

### Claim 10 (depends on 7)

The semiconductor device according to claim 7, wherein the second electrode comprises a single-layer structure.

### Claim 11 (depends on 7)

The semiconductor device according to claim 7, wherein the second electrode comprises a multilayer structure.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein the second electrode comprises:
a first conductive layer, wherein a material of the first conductive layer comprises a doped semiconductor material; and
a second conductive layer located between the first conductive layer and the insulating layer, wherein a material of the second conductive layer comprises titanium, titanium nitride, or a combination thereof.

### Claim 13 (depends on 7)

The semiconductor device according to claim 7, further comprising:
a dielectric layer located on the planarization layer.

### Claim 14 (depends on 7)

The semiconductor device according to claim 7, further comprising:
a first barrier layer located between the first contact and the second electrode; and
a second barrier layer located between the second contact and the substrate.