# US 12,016,171 B2 · Semiconductor device and method for fabricating the same

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- Number: US 12,016,171 B2
- Document ID: US12016171B2
- Status: Granted
- Kind: B2
- Application number: 17/978,344
- Filed: 2022-11-01
- Published: 2023-02-16
- Granted: 2024-06-18
- Earliest claimed: 2020-07-09
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Se Han Kwon
- Web page: https://patentgrep.com/patent/US12016171B2

## CPC

- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10W 20/0698: {Local interconnections}
- H10W 20/076: {in via holes or trenches}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W 20/48: Insulating materials thereof
- H10B 12/482: {Bit lines}
- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and method for fabricating the semiconductor device, which secure an overlay margin between the storage node and the storage node contact plug, as well as a processing margin, by excluding the connecting structure between the storage node and the storage node contact plug. A semiconductor device comprises a storage node contact hole provided between bit line structures, a first plug filling a lower portion of the storage node contact hole, a second plug protruding from the first plug, an insulation layer spacer covering a side wall of the second plug, and a storage node positioned at a higher level than the second plug and including an extension contacting another side wall of the second plug and a portion of a top surface of the first plug.

## Claims

### Claim 1

A semiconductor device, comprising:
a storage node contact hole provided between bit line structures;
a first plug tilling a lower portion of the storage node contact hole;
a second plug protruding from the first plug;
an insulation layer spacer partially covering a side wall of the second plug and partially exposing the side wall of the second plug; and
a storage node having an extension contacting the exposed side wall of the second plug.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the insulation layer spacer includes a first portion having a top surface positioned at the same level as a top surface of the second plug and a second portion having a top surface positioned at a lower level than the top surface of the second plug.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the extension has the same width as the storage node.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a bottom surface of the extension is positioned at a lower level than a top surface of the second plug.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a portion of a bottom surface of the extension contacts a second portion of the insulation layer spacer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the second plug is smaller in width than the first plug.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second plug protrudes from the first plug in a vertical direction.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein two opposite side walls of the second plug are spaced apart from two opposite side walls of the storage node contact hole.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first plug includes a stacked structure of a silicon-containing layer and a metal-containing layer or a stacked structure of a silicon-containing layer, metal silicide, and a metallic material.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the metallic material includes titanium nitride or tungsten.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the second plug includes a metallic material.