# US 12,016,170 B2 · Fin cut and fin trim isolation for advanced integrated circuit structure fabrication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,016,170 B2 - Document ID: US12016170B2 - Status: Granted - Kind: B2 - Application number: 18/124,936 - Filed: 2023-03-22 - Published: 2023-07-20 - Granted: 2024-06-18 - Earliest claimed: 2017-11-30 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Tahir Ghani; Byron Ho; Curtis W. Ward; Michael L. Hattendorf; Christopher P. Auth - Web page: https://patentgrep.com/patent/US12016170B2 ## CPC - H10B 10/15: {comprising a resistor load element} - H10B 10/125: {the MOSFET being a thin film transistor [TFT]} - H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins} - H10D 30/6213: {having rounded corners} - H10D 30/795: {being in lateral device isolation regions, e.g. STI} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants} - H10D 84/853: {comprising FinFETs} - H10D 88/00: Three-dimensional [3D] integrated devices - H10D 30/0212: {using self-aligned silicidation} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D 84/014: {the gate conductors having different materials or different implants} - H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin. ## Claims ### Claim 1 An integrated circuit structure, comprising: a discrete three-dimensional body comprising silicon, the discrete three-dimensional body having a channel region, and the discrete three-dimensional body having a longest dimension along a first direction; an isolation structure separating a first end of a first portion of the discrete three-dimensional body from a first end of a second portion of the discrete three-dimensional body along the first direction, the isolation structure having a width along the first direction, wherein the isolation structure is on a portion of the first portion of the discrete three-dimensional body; a first gate structure completely surrounding the channel region of the first portion of the discrete three-dimensional body, wherein the first gate structure has the width along the first direction, and wherein a center of the first gate structure is spaced apart from a center of the isolation structure by a pitch along the first direction; and a second gate structure over a second end of the first portion of the discrete three-dimensional body, the second end opposite the first end, the second gate structure having the width along the first direction, wherein a center of the second gate structure is spaced apart from the center of the gate first structure by the pitch along the first direction, wherein the second gate structure is completely surrounding a portion of the first portion of the discrete three-dimensional body. ### Claim 2 (depends on 1) The integrated circuit structure of claim 1, wherein the first gate structure and the second gate structure comprise a same conductive material. ### Claim 3 (depends on 1) The integrated circuit structure of claim 1, wherein the first end of the first portion of the discrete three-dimensional body has a surface roughness, and the second end of the first portion of the discrete three-dimensional body has a surface roughness less than the surface roughness of the first end of the first portion of the discrete three-dimensional body. ### Claim 4 (depends on 1) The integrated circuit structure of claim 1, wherein the first end of the first portion of the discrete three-dimensional body has a scalloped topography. ### Claim 5 (depends on 1) The integrated circuit structure of claim 1, further comprising: a first epitaxial semiconductor region on the first portion of the discrete three-dimensional body between the first gate structure and the isolation structure; and a second epitaxial semiconductor region on the first portion of the discrete three-dimensional body between the first gate structure and the second gate structure. ### Claim 6 (depends on 5) The integrated circuit structure of claim 5, wherein the first and second epitaxial semiconductor regions each have a width along a second direction orthogonal to the first direction, the width along the second direction wider than a width of the first portion of the discrete three-dimensional body along the second direction beneath the first gate structure. ### Claim 7 (depends on 1) The integrated circuit structure of claim 1, the first gate structure and the second gate structure each comprising a high-k dielectric layer between a gate electrode and the first portion of the discrete three-dimensional body, the high-k dielectric layer along sidewalls of the gate electrode. ### Claim 8 An integrated circuit structure, comprising: a discrete three-dimensional body comprising silicon, the discrete three-dimensional body having a channel region, and the discrete three-dimensional body having a longest dimension along a first direction; an isolation structure separating a first end of a first portion of the discrete three-dimensional body from a first end of a second portion of the discrete three-dimensional body along the first direction, the isolation structure having a width along the first direction, the first end of the first portion of the discrete three-dimensional body having a surface roughness; a gate structure comprising a gate electrode completely surrounding the channel region of the first portion of the discrete three-dimensional body, wherein the gate structure has the width along the first direction, and wherein a center of the gate structure is spaced apart from a center of the isolation structure by a pitch along the first direction; and a dummy gate structure over a second end of the first portion of the discrete three-dimensional body, the second end opposite the first end, the dummy gate structure having the width along the first direction, wherein a center of the dummy gate structure is spaced apart from the center of the gate structure by the pitch along the first direction, wherein the second end of the first portion of the discrete three-dimensional body has a surface roughness less than the surface roughness of the first end of the first portion of the discrete three-dimensional body. ### Claim 9 (depends on 8) The integrated circuit structure of claim 8, wherein the first end of the first portion of the discrete three-dimensional body has a scalloped topography. ### Claim 10 (depends on 8) The integrated circuit structure of claim 8, further comprising: a first epitaxial semiconductor region on the first portion of the discrete three-dimensional body between the gate structure and the isolation structure; and a second epitaxial semiconductor region on the first portion of the discrete three-dimensional body between the gate structure and the dummy gate structure. ### Claim 11 (depends on 10) The integrated circuit structure of claim 10, wherein the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, the width along the second direction wider than a width of the first portion of the discrete three-dimensional body along the second direction beneath the gate structure. ### Claim 12 (depends on 8) The integrated circuit structure of claim 8, the gate structure further comprising a high-k dielectric layer between the gate electrode and the first portion of the discrete three-dimensional body and along sidewalls of the gate electrode. ### Claim 13 An integrated circuit structure, comprising: a discrete three-dimensional body comprising silicon, the discrete three-dimensional body having a channel region, and the discrete three-dimensional body having a longest dimension along a first direction; an isolation structure separating a first end of a first portion of the discrete three-dimensional body from a first end of a second portion of the discrete three-dimensional body along the first direction, the isolation structure having a width along the first direction, the first end of the first portion of the discrete three-dimensional body having a surface roughness; a gate structure comprising a gate electrode completely surrounding the channel region of the first portion of the discrete three-dimensional body, wherein the gate structure has the width along the first direction, and wherein a center of the gate structure is spaced apart from a center of the isolation structure by a pitch along the first direction; and a dummy gate structure over a second end of the first portion of the discrete three-dimensional body, the second end opposite the first end, the dummy gate structure having the width along the first direction, wherein a center of the dummy gate structure is spaced apart from the center of the gate structure by the pitch along the first direction, wherein the dummy gate structure has a composition different than a composition of the gate structure. ### Claim 14 (depends on 13) The integrated circuit structure of claim 13, wherein the dummy gate structure comprises polycrystalline silicon. ### Claim 15 (depends on 13) The integrated circuit structure of claim 13, wherein the dummy gate structure comprises a silicon nitride pillar. ### Claim 16 (depends on 13) The integrated circuit structure of claim 13, wherein the gate structure further comprises a high-k dielectric layer between the gate electrode and the first portion of the discrete three-dimensional body and along sidewalls of the gate electrode. ### Claim 17 (depends on 13) The integrated circuit structure of claim 13, wherein the second end of the first portion of the discrete three-dimensional body has a surface roughness less than the surface roughness of the first end of the first portion of the discrete three-dimensional body.