Optimized static random access memory

A memory device comprising:

• a memory array comprising a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
• a substrate having a front side and a back side, wherein a transistor of the memory cell is formed on the front side, and wherein the back side is opposite of the front side;
• a first interconnect layer on the front side to provide a first bit line portion of the memory cell;
• a second interconnect layer on the front side to provide a second bit line portion of the memory cell;
• a third interconnect layer on the front side to provide a first word line of the memory cell;
• and
• a fourth interconnect layer on the front side to provide a second word line of the memory cell;
• a fifth interconnect layer on the back side to provide a ground voltage to the memory device,
• wherein each of the first interconnect layer and the second interconnect layer has a width that is greater than the width of each of the third interconnect layer and the fourth interconnect layer;
• wherein the first bit line portion abuts a first adjacent bit line portion of a first adjacent memory cell and the second bit line portion abuts a second adjacent bit line portion of a second adjacent memory cell;
• and
• wherein the fifth interconnect layer is wider than each of the first interconnect layer, the second interconnect layer, the third interconnect layer, and the fourth interconnect layer.

A memory device comprising:

• a memory array comprising a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
• a substrate having a front side and a back side, wherein a plurality of active regions are formed on the front side, and wherein the back side is opposite of the front side;
• a first interconnect layer on the back side to provide a supply voltage to the memory cell;
• a second interconnect layer on the back side to provide a ground voltage to the memory cell;
• a third interconnect layer on the front side to provide a bit line of the memory cell;
• a fourth interconnect layer on the front side to provide a word line of the memory cell;
• a first interconnect structure that connects the first interconnect layer to a first active region of the plurality of active regions on the front side;
• and
• a second interconnect structure that connects the second interconnect layer to a second active region of the plurality of active regions on the front side;
• wherein the third interconnect layer corresponds to a first bit line portion of the bit line that abuts a second bit line portion of an adjacent memory cell,
• wherein the first interconnect layer is wider than each of the third interconnect layer and the fourth interconnect layer;
• and
• wherein the second interconnect layer is wider than each of the third interconnect layer and the fourth interconnect layer.