# US 12,016,130 B2 · Method of manufacturing printed circuit board > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,016,130 B2 - Document ID: US12016130B2 - Status: Granted - Kind: B2 - Application number: 17/683,604 - Filed: 2022-03-01 - Published: 2022-12-01 - Granted: 2024-06-18 - Earliest claimed: 2021-05-26 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Applicants: Samsung Electro-Mechanics Co., Ltd. - Inventors: Chan Jin Park; Jong Eun Park; Hyun Seok Yang; Sangik Cho; Hiroki Okada; Young Ook Cho; Mi Jeong Jeon; In Jae Chung - Web page: https://patentgrep.com/patent/US12016130B2 ## CPC - H05K 3/108: {by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241)} - H05K 3/188: {by direct electroplating} - C25D 5/022: {using masking means} - C25D 7/00: Electroplating characterised by the article coated - G03F 7/20: Exposure; Apparatus therefor (photographic printing apparatus for making copies G03B27/00) - H05K 3/4682: {Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil} - H05K 2203/025: Abrading, e.g. grinding or sand blasting - H05K 2203/1476: Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) ## Abstract A method of manufacturing a printed circuit board includes: forming a resist layer; exposing first areas of the resist layer spaced apart from each other; after exposing the first areas, exposing second areas of the resist layer, the second areas being spaces between the first areas; forming first and second openings spaced apart from each other in the first and second areas by developing the resist layer; and forming a plurality of conductor patterns by filling the first and second openings with conductors. ## Claims ### Claim 1 A method of manufacturing a printed circuit board, the method comprising: forming a resist layer; exposing first areas of the resist layer spaced apart from each other; after exposing the first areas, exposing second areas of the resist layer, the second areas being spaces between the first areas; forming first and second openings spaced apart from each other in the first and second areas by developing the resist layer; and forming a plurality of conductor patterns by filling the first and second openings with conductors, wherein the first openings include a 1-1st opening and a 1-2nd opening spaced apart from each other, the second openings include a 2-1st opening and a 2-2nd opening spaced apart from each other, the plurality of conductor patterns include a 1-1st conductor pattern formed in the 1-1st opening, a 1-2nd conductor pattern formed in the 1-2nd opening, a 2-1st conductor pattern formed in the 2-1st opening, and a 2-2nd conductor pattern formed in the 2-2nd opening, when the plurality of conductor patterns are taken in cross sections thereof in a thickness direction, each of WP1-1, WP1-2, WP2-1, and WP2-2 is 0.5 μm or more and 5 μm less, where WP1-1 is an average line width of the 1-1st conductor pattern, WP2-1 is an average line width of the 2-1st conductor pattern, WP1-2 is an average line width of the 1-2nd conductor pattern, and WP2-2 is an average line width of the 2-2nd conductor pattern, and a ratio of a width of each of spaces between the 1-1st, 2-1st, 1-2nd, and 2-2nd conductor patterns with respect to an average height of the 1-1st, 2-1st, 1-2nd, and 2-2nd conductor patterns is more than ¼ and less than ⅗. ### Claim 2 (depends on 1) The method of claim 1, wherein in the exposing of the second areas of the resist layer, the second areas are exposed so that the first areas are included in non-exposed areas between the second areas spaced apart from each other. ### Claim 3 (depends on 2) The method of claim 2, further comprising forming a seed layer before the forming of the resist layer, wherein the forming of the plurality of conductor patterns includes: forming a plating layer on the seed layer exposed through the first and second openings by electroplating; removing the resist layer; and removing the seed layer. ### Claim 4 (depends on 3) The method of claim 3, wherein the forming of the plating layer on the seed layer exposed through the first and second openings by electroplating includes: performing over-plating so that the plating layer exceeds a thickness of the resist layer; and polishing an over-plated area of the plating layer exceeding the thickness of the resist layer. ### Claim 5 (depends on 3) The method of claim 3, wherein the seed layer is a metal layer attached onto one surface of an insulating material, the resist layer is formed on the metal layer, the forming of the plurality of conductor patterns further includes forming an insulating layer on the metal layer to cover the plating layer between the removing of the resist layer and the removing of the seed layer, and the removing of the seed layer includes: removing the insulating material from the metal layer; and removing the metal layer attached onto the insulating layer. ### Claim 6 (depends on 1) The method of claim 1, wherein the second areas and the first areas are alternately disposed. ### Claim 7 (depends on 1) The method of claim 1, wherein when the plurality of conductor patterns are taken in the cross sections thereof in the thickness direction, each of S1 to S3 is 0.5 μm or more and 5 μm or less, where S1 is an average space between the 1-1st conductor pattern and the 2-1st conductor pattern, S2 is an average space between the 2-1st conductor pattern and the 1-2nd conductor pattern, and S3 is an average space between the 1-2nd conductor pattern and the 2-2nd conductor pattern. ### Claim 8 (depends on 7) The method of claim 7, wherein S1 and S3 satisfy 0.9