# US 12,016,128 B2 · Circuit board and method of manufacturing the same

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- Number: US 12,016,128 B2
- Document ID: US12016128B2
- Status: Granted
- Kind: B2
- Application number: 17/462,157
- Filed: 2021-08-31
- Published: 2022-03-03
- Granted: 2024-06-18
- Earliest claimed: 2020-09-03
- Assignees: LG Innotek Co., Ltd.
- Applicants: LG Innotek Co., Ltd.
- Inventors: Min Young Hwang; Byeong Kyun Choi; Jin Seok Lee; Moo Seong Kim
- Web page: https://patentgrep.com/patent/US12016128B2

## CPC

- H05K 3/10: in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K 3/427: {initial plating of through-holes in metal-clad substrates}
- H05K 1/09: Use of materials for the {conductive, e.g. } metallic pattern
- H05K 1/0373: {containing additives, e.g. fillers (H05K1/036 takes precedence)}
- H05K 3/24: Reinforcing of the conductive pattern {(by solder coating H05K3/3465)}
- H05K 2201/0209: Inorganic, non-metallic particles
- H05K 2201/0355: Metal foils
- H05K 2201/0358: Resin coated copper [RCC]
- H05K 2201/0959: Plated through-holes or plated blind vias filled with insulating material
- H05K 2203/0723: Electroplating, e.g. finish plating
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A circuit board according to an embodiment includes an insulating layer; and a circuit pattern disposed on the insulating layer, wherein the circuit pattern includes a copper foil layer disposed on the insulating layer, a first plating layer disposed on the copper foil layer, and a second plating layer disposed on the first plating layer, and wherein the copper foil layer has a thickness in a range of 2 μm to 5 μm.

## Claims

### Claim 1

A circuit board comprising:
an insulating layer;
a circuit pattern disposed on the insulating layer; and
a via disposed in a via hole passing through the insulating layer,
wherein the circuit pattern includes:
a copper foil layer disposed on the insulating layer,
a first plating layer disposed on the copper foil layer, and
a second plating layer disposed on the first plating layer, and
wherein the insulating layer includes a resin and a filler in the resin, and
wherein a recess is provided at an inner wall of the via hole and has a shape corresponding to the filler.

### Claim 2 (depends on 1)

The circuit board of claim 1, wherein the insulating layer and the copper foil layer are a resin coated copper (RCC).

### Claim 3 (depends on 1)

The circuit board of claim 1, the copper foil layer has a 10-point average roughness (Rz) in a range of 1.5 μm to 3.0 μm.

### Claim 4 (depends on 1)

The circuit board of claim 1, the first plating layer has a thickness in a range of 1 μm to 2.5 μm.

### Claim 5 (depends on 1)

The circuit board of claim 1, wherein the second plating layer has a thickness in a range of 10 μm to 25 μm.

### Claim 6 (depends on 1)

The circuit board of claim 1,
wherein the via contacts the resin and does not contact the filler.

### Claim 7 (depends on 1)

The circuit board of claim 1, wherein a thickness of the copper foil layer is different from a thickness of the first plating layer.

### Claim 8 (depends on 1)

The circuit board of claim 1, wherein the recess has a depth in a range of 0.5 μm to 1.0 μm.

### Claim 9 (depends on 7)

The circuit board of claim 7,
wherein the recess has a width corresponding to a diameter of the filler.

### Claim 10 (depends on 9)

The circuit board of claim 9, wherein the diameter of the filler has a range of 0.5 μm to 1.0 μm.

### Claim 11 (depends on 9)

The circuit board of claim 9, wherein an area of the recess is 3% to 10% of a total area of inner wall of the via hole.

### Claim 12 (depends on 11)

The circuit board of claim 11, wherein the inner wall of the via hole has a surface roughness (Ra) in a range of 0.5 μm to 1.0 μm,
wherein the via has a surface roughness corresponding to the inner wall of the via hole.

### Claim 13 (depends on 1)

The circuit board of claim 1, wherein the via comprises:
a first via layer corresponding to the first plating layer; and
a second via layer corresponding to the second plating layer.

### Claim 14 (depends on 7)

The circuit board of claim 7, wherein the thickness of the copper foil layer is greater than the thickness of the first plating layer.

### Claim 15 (depends on 7)

The circuit board of claim 7, wherein the thickness of the copper foil layer has a range of 2 μm to 5 μm.

### Claim 16 (depends on 1)

The circuit board of claim 1, wherein the via includes a convex portion disposed in the recess of the via hole.