# US 12,016,118 B2 · Ceramic-based circuit board assemblies formed using metal nanoparticles > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,016,118 B2 - Document ID: US12016118B2 - Status: Granted - Kind: B2 - Application number: 17/760,079 - Filed: 2021-02-26 - Published: 2023-03-02 - Granted: 2024-06-18 - Earliest claimed: 2020-03-02 - Assignees: Kuprion Inc. - Applicants: Kuprion Inc. - Inventors: Alfred A. Zinn; Khanh Nguyen - Web page: https://patentgrep.com/patent/US12016118B2 ## CPC - H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass} - H05K 3/4629: {laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets} - H05K 1/092: {Dispersed materials, e.g. conductive pastes or inks} - H05K 1/097: {Inks comprising nanoparticles and specially adapted for being sintered at low temperature (H05K1/095 takes precedence)} - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 1/181: associated with surface mounted components - H05K 1/183: associated with components mounted in and supported by recessed areas of the PCBs - H05K 3/107: {by filling grooves in the support with conductive material (H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence)} - H05K 3/303: with surface mounted components (H05K3/32 takes precedence) - H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)} - H05K 3/46: Manufacturing multilayer circuits - H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards - H05K 2201/09227: Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting - H05K 2201/09563: Metal filled via - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract Printed circuit boards may be formed using ceramic substrates with high thermal conductivity to facilitate heat dissipation. Metal nanoparticles, such as copper nanoparticles, may be used to form conductive traces and fill through-plane vias upon the ceramic substrates. Multi-layer printed circuit boards may comprise two or more ceramic substrates adhered together, wherein each ceramic substrate has one or more conductive traces defined thereon and the one or more conductive traces are formed through consolidation of metal nanoparticles. The one or more conductive traces in a first ceramic substrate layer are in electrical communication with at least one second ceramic substrate layer adjacent thereto. ## Claims ### Claim 1 A method comprising: providing a ceramic substrate; forming one or more conductive traces upon the ceramic substrate by consolidating metal nanoparticles thereupon; and forming a multi-layer printed circuit board by adhering two or more ceramic substrates together; and wherein the one or more conductive traces in a first ceramic substrate layer are in electrical communication with at least one second ceramic substrate layer adjacent thereto; wherein one or more through-plane vias extend through the ceramic substrate, the method further comprising the steps of: filing the one or more through-plane vias with a conductive material, wherein the conductive material comprises metal nanoparticles; and consolidating the metal nanoparticles with the one or more through-plane vias to form the conductive material therein as a metal plug; and wherein the metal nanoparticles are consolidated to form the one more conductive traces and the metal plug within the one or more through-plane vias at substantially the same time. ### Claim 2 (depends on 1) The method of claim 1, wherein the one or more conductive traces are defined upon a surface plane of the ceramic substrate, in a groove defined upon the ceramic substrate, or any combination thereof. ### Claim 3 (depends on 1) The method of claim 1, wherein at least a portion of the through-plane vias establish the electrical communication between adjacent layers in the multi-layer printed circuit board. ### Claim 4 (depends on 1) The method of claim 1, wherein the metal nanoparticles comprise copper nanoparticles. ### Claim 5 (depends on 1) The method of claim 1, wherein a non-printed electronic component is disposed upon a surface plane of the ceramic substrate or within a groove or cavity upon the ceramic substrate, the non-printed electronic component being in electrical communication with the one or more conductive traces upon at least one ceramic substrate layer. ### Claim 6 (depends on 5) The method of claim 5, wherein the non-printed electronic component is disposed upon the surface plane of the ceramic substrate and bridges a gap extending between a first portion and a second portion of at least one conductive trace thereupon. ### Claim 7 (depends on 5) The method of claim 5, wherein the non-printed electronic component is disposed upon the surface plane of the ceramic substrate forming the first ceramic substrate layer and is housed within a groove or cavity defined upon the ceramic substrate forming an adjacent ceramic substrate layer. ### Claim 8 (depends on 1) The method of claim 1, wherein the one or more conductive traces are formed upon an adhesive layer or a bonding layer in contact with the ceramic substrate. ### Claim 9 A multi-layer printed circuit board (PCB) comprising: two or more ceramic substrates adhered together, each ceramic substrate having one or more conductive traces defined thereon; wherein the one or more conductive traces are formed through consolidation of metal nanoparticles; and wherein the one or more conductive traces in a first ceramic substrate layer are in electrical communication with at least one second ceramic substrate layer adjacent thereto; wherein one or more through-plane vias extend through the ceramic substrate, the one or more through-plane vias being filled with a conductive material; wherein the conductive material comprises a metal plug formed by consolidating metal nanoparticles within the one or more through-plane vias; and wherein the metal nanoparticles are consolidated to form the one more conductive traces and the metal plug within the one or more through-plane vias at substantially the same time. ### Claim 10 (depends on 9) The multi-layer printed circuit board of claim 9, wherein the one or more conductive traces are defined upon a surface plane of the ceramic substrate, in a groove defined upon the ceramic substrate, or any combination thereof. ### Claim 11 (depends on 9) The multi-layer printed circuit board of claim 9, wherein at least a portion of the through-plane vias establish electrical communication between adjacent ceramic substrate layers. ### Claim 12 (depends on 9) The multi-layer printed circuit board of claim 9, wherein the metal nanoparticles comprise copper nanoparticles. ### Claim 13 (depends on 9) The multi-layer printed circuit board of claim 9, wherein a non-printed electronic component is disposed upon a surface plane of the ceramic substrate or within a groove or cavity upon the ceramic substrate, the non-printed electronic component being in electrical communication with one or more conductive traces upon at least one ceramic substrate layer. ### Claim 14 (depends on 13) The multi-layer printed circuit board of claim 13, wherein the non-printed electronic component is disposed upon the surface plane of the ceramic substrate and bridges a gap extending between a first portion and a second portion of at least one conductive trace. ### Claim 15 (depends on 13) The multi-layer printed circuit board of claim 13, wherein the non-printed electronic component is disposed upon the surface plane of the ceramic substrate forming the first ceramic substrate layer and is housed within a groove or cavity defined upon the ceramic substrate forming an adjacent ceramic substrate layer. ### Claim 16 (depends on 9) The multi-layer printed circuit board of claim 9, wherein the one or more conductive traces are formed upon an adhesive layer or a bonding layer in contact with the ceramic substrate.