# US 12,015,419 B2 · Switched capacitor circuitry for mitigating pole-zero doublet errors in an analog circuit

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- Number: US 12,015,419 B2
- Document ID: US12015419B2
- Status: Granted
- Kind: B2
- Application number: 17/829,297
- Filed: 2022-05-31
- Published: 2023-12-14
- Granted: 2024-06-18
- Earliest claimed: 2022-05-31
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Roswald Francis
- Web page: https://patentgrep.com/patent/US12015419B2

## CPC

- H03M 1/1033: {over the full range of the converter, e.g. for correcting differential non-linearity}
- H03F 1/26: Modifications of amplifiers to reduce influence of noise generated by amplifying elements
- H03F 3/005: {using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence)}
- H03F 3/21: with semiconductor devices only {(H03F3/245 takes precedence)}
- H03M 1/124: {Sampling or signal conditioning arrangements specially adapted for A/D converters}
- H03F 2200/294: the amplifier being a low noise amplifier [LNA]
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03F: AMPLIFIERS

## Abstract

Examples describe a switched capacitor (SC) circuitry calibrated to mitigate the pole-zero (PZ) doublet errors that occur in an analog circuitry. Due to PZ-doublet errors, the slow settling time response of an input step function to an analog circuitry make it impractical to use in applications such as a digital oscilloscope. Mitigating the PZ-doublet errors in the frequency domain is not practical due to the problem of the generation of low frequency sinusoidal tones. The solution disclosed in the present invention is to apply a step function and examine the output's slow settling error waveform. A signal is input to an analog to digital converter, and the output of the converter is processed by a computation that produces calibration codes. Calibration codes are coupled to a SC circuitry to mitigate the PZ-doublet errors. The error waveform is then minimized within a specified accuracy.

## Claims

### Claim 1

An integrated circuit, comprising:
analog circuitry configured to receive an analog signal;
switched capacitor (SC) circuitry coupled to the analog circuitry;
analog to digital converter (ADC) circuitry connected to an analog output of the analog circuitry; and
logic circuitry coupled to an output of the ADC circuitry and configured to:
compute error mitigation codes based on ADC output data to mitigate pole-zero (PZ) doublet errors; and
transmit the error mitigation codes to calibrate the SC circuitry.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the logic circuitry is further configured to:
enter an iterative search loop, up to a maximum iteration value;
detect if the ADC output data is rising or falling;
if the ADC output data is falling:
measure a first ADC output data value after a falling edge of a square wave applied to the analog circuitry; and
measure a second ADC output data value before a rising edge of the square wave applied to the analog circuitry;
if the ADC output data is rising:
measure the first ADC output data value after the rising edge of the square wave applied to the analog circuitry; and
measure the second ADC output data value before the falling edge of the square wave applied to the analog circuitry;
compute a difference value between the first ADC output data value and the second ADC output data value;
compare the difference value to a maximum error value;
compute a new calibration code based on the difference value; and
perform repeated iterations of the iterative search loop to compute a final error mitigation code.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the error mitigation codes include calibration trim bits.

### Claim 4

An error mitigation system, comprising:
analog circuitry configured to receive an analog signal at an analog input;
switched capacitor (SC) circuitry coupled to the analog circuitry;
analog to digital converter (ADC) circuitry, coupled to the analog circuitry, producing ADC output data; and
logic circuitry coupled to the ADC circuitry configured to:
compute error mitigation codes to mitigate pole-zero (PZ) doublet errors; and
transmit the error mitigation codes to calibrate the SC circuitry.

### Claim 5 (depends on 4)

The error mitigation system of claim 4, wherein the error mitigation codes include calibration trim bits.

### Claim 6 (depends on 4)

The error mitigation system of claim 4, further comprising:
a first SC circuitry, of the SC circuitry, connected between a first control device and the analog input;
a second SC circuitry, of the SC circuitry, connected between a second control device and the analog input; and
an analog output.

### Claim 7 (depends on 6)

The error mitigation system of claim 6, further comprising:
a first control input on the first control device; and
a second control input on the second control device.

### Claim 8 (depends on 7)

The error mitigation system of claim 7, wherein:
the first SC circuitry is coupled to the first control input; and
the second SC circuitry is coupled to the second control input.

### Claim 9 (depends on 8)

The error mitigation system of claim 8, wherein:
the first control device comprises a first transistor; and
the second control device comprises a second transistor.

### Claim 10 (depends on 9)

The error mitigation system of claim 9, wherein:
the first transistor comprises a first drain, a first control gate, and a first source; and
the second transistor comprises a second drain, a second control gate, and a second source.

### Claim 11 (depends on 10)

The error mitigation system of claim 10, wherein:
the first control input comprises the first control gate of the first transistor;
a second control input comprises the second control gate of the second transistor; and
the analog output is connected to the first drain of the first transistor and to the second drain of the second transistor.

### Claim 12 (depends on 4)

The error mitigation system of claim 4, wherein the logic circuitry is further configured to:
compute an initial midcode calibration code;
apply the midcode calibration code to the SC circuitry;
enter an iterative search loop, up to a maximum iteration value;
within the iterative search loop, repeatedly measure SC circuitry error values; and
within the iterative search loop, repeatedly adjust a calibration code until a final SC circuitry error value is less than a maximum error value.

### Claim 13 (depends on 12)

The error mitigation system of claim 12, wherein the logic circuitry is further configured to:
enter an iterative search loop, up to a maximum iteration value;
detect a rising or falling edge of the ADC output data;
if the ADC output data is falling:
measure a first ADC output data value after a falling edge of a square wave applied to the analog circuitry; and
measure a second ADC output data value before a rising edge of the square wave applied to the analog circuitry;
if the ADC output data is rising:
measure the first ADC output data value after the rising edge of the square wave applied to the analog circuitry; and
measure the second ADC output data value before the falling edge of the square wave applied to the analog circuitry;
compute a difference value between the first ADC output data value and the second ADC output data value;
compare the difference value to a maximum error value;
compute a new calibration code based on the difference value; and
perform repeated iterations of the iterative search loop to compute a final error mitigation code.

### Claim 14

A method for mitigating errors, comprising:
providing switched capacitor (SC) circuitry coupled to an input of analog to digital converter (ADC) circuitry;
receiving output data from the ADC circuitry;
computing error mitigation codes based on the output data to mitigate pole-zero (PZ) doublet errors; and
transmitting the error mitigation codes to the SC circuitry to calibrate the SC circuitry.

### Claim 15 (depends on 14)

The method of claim 14 for mitigating errors wherein the error mitigation codes include calibration trim bits.

### Claim 16 (depends on 14)

The method of claim 14 for mitigating errors, further comprising:
providing analog circuitry coupled to the ADC circuitry;
providing SC error mitigating circuitry coupled to the analog circuitry;
providing ADC output data; and
providing logic circuitry configured to compute SC circuitry error mitigation codes.

### Claim 17 (depends on 16)

The method of claim 16 for mitigating errors, further comprising:
computing an initial midcode calibration code;
applying the midcode calibration code to the SC circuitry;
entering iterative search loops, up to a maximum iteration value;
within the iterative search loops, repeatedly measuring SC circuitry error values; and
within the iterative search loops, repeatedly adjusting error mitigation codes until a final error value is less than a maximum error value.

### Claim 18 (depends on 17)

The method of claim 17 for mitigating errors, further comprising:
measuring a first output data value;
measuring a second output data value;
computing a difference value between the first output data value and the second output data value;
comparing the difference value to a maximum error value;
computing a new calibration code based on the difference value; and
performing repeated iterations to compute a final error mitigation code.

### Claim 19 (depends on 14)

The method of claim 14 for mitigating errors, further comprising:
injecting a square wave into analog circuitry coupled to the SC circuitry;
computing a midcode calibration code;
applying the midcode calibration code to the SC circuitry;
providing a maximum iteration value;
initializing an iteration integer and entering an iteration loop;
detecting if an output data value is rising or falling;
if the output data value is rising:
computing a first calibration code by measuring the output data value after a rising edge of the square wave; and
computing a second calibration code by measuring the output data value before a falling edge of the square wave;
computing a difference value by subtracting the first calibration code from the second calibration code;
computing a new calibration code based on the difference value;
repeating the iteration loop while a maximum error value and the difference value are not equal;
incrementing the iteration integer; and
exiting the iteration loop when the iteration integer equals the maximum iteration value.

### Claim 20 (depends on 14)

The method of claim 14 for mitigating errors, further comprising:
computing a midcode calibration code;
applying the midcode calibration code to the SC circuitry;
injecting a square wave into the analog;
providing a maximum iteration value;
initializing an iteration integer and entering an iteration loop;
detecting if an output data value is rising or falling;
if the output data value is falling:
computing a first calibration code by measuring the output data value after a falling edge of the square wave; and
computing a second calibration code by measuring the output data value before a rising edge of the square wave;
computing a difference value by subtracting the second calibration code from the first calibration code;
computing a new calibration code based on the difference value;
repeating the iteration loop while a maximum error value and the difference value are not equal;
incrementing the iteration integer; and
exiting the iteration loop when the iteration integer equals the maximum iteration value.