# US 12,015,415 B1 · High gain low power phase detector and loop filter for phase lock loop (PLL) > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,015,415 B1 - Document ID: US12015415B1 - Status: Granted - Kind: B1 - Application number: 18/086,565 - Filed: 2022-12-21 - Published: 2024-06-27 - Granted: 2024-06-18 - Earliest claimed: 2022-12-21 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Sungmin Ock; Marzio Pedrali-Noy - Web page: https://patentgrep.com/patent/US12015415B1 ## CPC - H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) - H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump} - H03L 7/0992: {comprising a counter or a frequency divider} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract An apparatus including: a phase lock loop (PLL), including: a phase detector and loop pass filter (PD/LF), including: a phase/frequency detector including a first input configured to receive a reference signal, and a second input configured to receive a feedback signal, and an output configured to produce an output signal based on the reference and feedback signals; a first capacitor; and a charge pump, including: a charging path configured to generate a charging current to charge the first capacitor based on the output signal; and a discharging path including a first resistor configured to discharge the first capacitor. ## Claims ### Claim 1 An apparatus, comprising: a phase lock loop (PLL), comprising: a phase detector and loop pass filter (PD/LF), comprising: a phase/frequency detector including a first input configured to receive a reference signal, and a second input configured to receive a feedback signal, and an output configured to produce an output signal based on the reference and feedback signals; a first capacitor; a charge pump, comprising: a charging path configured to generate a charging current to charge the first capacitor based on the output signal, wherein the charging path comprises a first field effect transistor (FET) coupled between an upper voltage rail and a first node; and a discharging path including a first resistor configured to discharge the first capacitor, wherein the discharging path comprises the first resistor and a second FET coupled in series between the first node and a lower voltage rail, wherein gates of the first and second FETs are coupled to the output of the phase/frequency detector and a first switching device coupled between the first node and a second node, wherein the first capacitor is coupled between the second node and the lower voltage rail. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first resistor comprises a variable resistor. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the discharging path is configured to partially discharge the first capacitor during a discharging phase. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the charging path further comprises a second resistor coupled between the first FET and the first node. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the second resistor comprises a variable resistor. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the PD/LF further comprises: a second switching device coupled between the second node and a third node; and a second capacitor coupled between the third node and the lower voltage rail. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the PD/LF further comprises a non-overlapping clock generator configured to generate: a non-complementary clock signal based on the feedback signal, wherein the non-complementary clock signal controls an on/off state of the first switching device; and a complementary clock signal based on the feedback signal, wherein the complementary clock signal controls an off/off state of the second switching device. ### Claim 8 (depends on 6) The apparatus of claim 6, wherein the PLL further comprises a voltage controlled oscillator (VCO) coupled to the third node. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the PLL further comprises a frequency divider configured to generate the feedback signal based on a VCO signal generated by the VCO. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the phase/frequency detector comprises an exclusive NOR gate. ### Claim 11 An apparatus, comprising: a phase lock loop (PLL), comprising: a phase detector and loop pass filter (PD/LF), comprising: a phase/frequency detector including a first input configured to receive a reference signal, and a second input configured to receive a feedback signal, and an output configured to produce an output signal based on the reference and feedback signals; a first capacitor; and a charge pump, comprising: a charging path configured to generate a charging current to charge the first capacitor based on the output signal, the charging path comprises a current source and a first switching device coupled in series between an upper voltage rail and a first node, wherein an on/off state of the first switching device is controlled by the output signal of the phase/frequency detector, and wherein the first capacitor is coupled between the first node and the lower voltage rail; and a discharging path including a first resistor configured to discharge the first capacitor, the discharging path comprises the first resistor and a second switching device coupled in series between the first node and a lower voltage rail. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the PD/LF further comprises: a third switching device coupled between the first node and a second node; and a second capacitor coupled between the second node and the lower voltage rail. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein: the PD/LF further comprises a control circuit configured to generate a first control signal and a second control signal, wherein the first and second control signals are based on the reference signal; an on/off state of the second switching device is controlled by the first control signal; and an on/off state of the third switching device is controlled by the second control signal. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the PLL further comprises a voltage controlled oscillator (VCO) coupled to the second node. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the PLL further comprises a frequency divider configured to generate the feedback signal based on a VCO signal generated by the VCO. ### Claim 16 A method of generating a frequency control signal for a voltage controlled oscillator (VCO), comprising: generating a phase difference signal based on a reference signal and a feedback signal, wherein the feedback signal is based on a VCO signal generated by the VCO; partially discharging a first capacitor from a first voltage to a second voltage above ground potential during a discharging phase; charging the first capacitor from the second voltage to a third voltage based on the phase difference signal during a charging phase, wherein the frequency control signal is based on the third voltage; and distributing a charge on the first capacitor with a second capacitor when the first capacitor is charged to the third voltage, to form a fourth voltage across the first and second capacitors, wherein the frequency control signal is based on the fourth voltage. ### Claim 17 (depends on 16) The method of claim 16, further comprising controlling the partial discharging of the first capacitor including controlling a resistance of a discharge path between the first capacitor and ground. ### Claim 18 (depends on 16) The method of claim 16, further comprising controlling the charging of the first capacitor including controlling a resistance of a charging path between an upper voltage rail and the first capacitor. ### Claim 19 (depends on 16) The method of claim 16, further comprising controlling the partial discharging of the first capacitor based on the phase difference signal. ### Claim 20 An apparatus of generating a frequency control signal for a voltage controlled oscillator (VCO), comprising: means for generating a phase difference signal based on a reference signal and a feedback signal, wherein the feedback signal is based on a VCO signal generated by the VCO; means for partially discharging a first capacitor from a first voltage to a second voltage above ground potential during a discharging phase; means for charging the first capacitor from the second voltage to a third voltage based on the phase difference signal during a charging phase, wherein the frequency control signal is based on the third voltage; and means for distributing a charge on the first capacitor with a second capacitor when the first capacitor is charged to the third voltage, to form a fourth voltage across the first and second capacitors, wherein the frequency control signal is based on the fourth voltage. ### Claim 21 (depends on 20) The apparatus of claim 20, further comprising means for controlling the partial discharging of the first capacitor including controlling a resistance of a discharge path between the first capacitor and ground. ### Claim 22 (depends on 20) The apparatus of claim 20, further comprising means for controlling the charging of the first capacitor including controlling a resistance of a charging path between an upper voltage rail and the first capacitor. ### Claim 23 (depends on 20) The apparatus of claim 20, further comprising means for controlling the partial discharging of the first capacitor based on the phase difference signal.