# US 12,015,414 B2 · Dual digital phase lock loop with unmodulation coupling

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- Number: US 12,015,414 B2
- Document ID: US12015414B2
- Status: Granted
- Kind: B2
- Application number: 17/961,741
- Filed: 2022-10-07
- Published: 2024-04-11
- Granted: 2024-06-18
- Earliest claimed: 2022-10-07
- Assignees: Renesas Electronics America Inc.
- Applicants: Renesas Electronics America Inc.
- Inventors: Menno Tjeerd Spijker
- Web page: https://patentgrep.com/patent/US12015414B2

## CPC

- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H03L 7/1075: {by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence)}
- H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider}
- H03L 7/23: with pulse counters or frequency dividers
- H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Semiconductor devices for synchronizing networks are described. A semiconductor device can include an analog phase-lock loop (APLL) configured to output a first signal. The semiconductor device can further include a first digital phase-lock loop (DPLL) configured to output a second signal. The semiconductor device can further include a second DPLL configured to output a third signal. A combination of the first signal and the second signal can be used to generate a first output clock signal. A difference resulting from a subtraction of the second signal from the third signal can be used to generate a second output clock signal.

## Claims

### Claim 1

A semiconductor device comprising:
an analog phase-lock loop (APLL) configured to output a first signal;
a first digital phase-lock loop (DPLL) configured to output a second signal; and
a second DPLL configured to output a third signal, wherein:
a combination of the first signal and the second signal is being used to generate a first output clock signal; and
a difference resulting from a subtraction of the second signal from the third signal is being used to generate a second output clock signal.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
an integer divider configured to:
receive the combination of the first signal and the second signal; and
output the first output clock signal; and
a fractional output divider configured to:
receive the difference and the combination; and
output the second output clock signal.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising a plurality of fractional output dividers, wherein each one of the plurality of fractional output dividers is configured to output a copy of the second output clock signal.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising a low pass filter configured to filter the second signal prior to the subtraction of the second signal from the third signal, where a bandwidth of the low pass filter is based on a bandwidth of the APLL.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a scaler configured to scale the difference before generation of the second output clock signal.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a frequency output divider, wherein frequency output divider comprises:
a multi-modulus divider configured to receive the combination of the first signal and the second signal;
a sigma-delta modulator configured to receive the difference combination of the first signal and the second signal; and
a jitter reduction circuit configured to reduce jitter in the second output clock signal.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a difference between a bandwidth of the first DPLL and a bandwidth of the second DPLL is less than a predefined threshold.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the second output clock signal is independent from operations of the first DPLL.

### Claim 9

An apparatus comprising:
a plurality of transceivers;
a timing circuit configured to:
receive a first reference signal from a first transceiver among the plurality of transceivers;
receive a second reference signal from a second transceiver among the plurality of transceivers;
output a first output clock signal to a second transceiver among the plurality of transceivers; and
output a second output clock signal to a second clock circuit among the plurality of clock circuits,
wherein:
the first output clock signal is based on a combination of a first signal generate by an analog phase-lock loop (APLL) and a second signal generated by a first digital phase-lock loop (DPLL) in the timing circuit; and
the second output clock signal is based on a difference resulting from a subtraction of the second signal from a third signal generates by a second DPLL of the timing circuit.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the timing circuit comprises:
an integer divider configured to:
receive the combination of the first signal and the second signal; and
output the first output clock signal; and
a fractional output divider configured to:
receive the difference and the combination; and
output the second output clock signal.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the timing circuit comprises a plurality of fractional output dividers, and each one of the plurality of fractional output dividers is configured to output a copy of the second output clock signal.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the timing circuit comprises a low pass filter configured to filter the second signal prior to the subtraction of the second signal from the third signal, where a bandwidth of the low pass filter is based on a bandwidth of the APLL.

### Claim 13 (depends on 9)

The apparatus of claim 9, wherein the timing circuit comprises a scaler configured to scale the difference before generation of the second output clock signal.

### Claim 14 (depends on 9)

The apparatus of claim 9, wherein the timing circuit comprises a frequency output divider, wherein frequency output divider comprises:
a multi-modulus divider configured to receive the combination of the first signal and the second signal;
a sigma-delta modulator configured to receive the difference combination of the first signal and the second signal; and
a jitter reduction circuit configured to reduce jitter in the second output clock signal.

### Claim 15 (depends on 9)

The apparatus of claim 9, wherein a difference between a bandwidth of the first DPLL and a bandwidth of the second DPLL is less than a predefined threshold.

### Claim 16 (depends on 9)

The apparatus of claim 9, wherein the second output clock signal is independent from the first reference signal.

### Claim 17

A method for operating a timing circuit to synchronize a plurality of networks, the method comprising:
operating an analog phase-lock loop (APLL) to output a first signal;
operating a first digital phase-lock loop (DPLL) to output a second signal;
operating a second DPLL to output a third signal;
combining the first signal and the second signal to generate a first output clock signal; and
subtracting the second signal from the third signal to generate a second output clock signal, wherein the second output clock signal is independent from operations of the first DPLL.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
operating a plurality of fractional output dividers to output a plurality of copies of the second output clock signal.

### Claim 19 (depends on 17)

The method of claim 17, further comprising operating a low pass filter to filter the second signal prior to subtracting of the second signal from the third signal, wherein a bandwidth of the low pass filter is based on a bandwidth of the APLL.

### Claim 20 (depends on 17)

The method of claim 17, wherein a difference between a bandwidth of the first DPLL and a bandwidth of the second DPLL is less than a predefined threshold.