# US 12,015,411 B2 · Testable time-to-digital converter

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- Number: US 12,015,411 B2
- Document ID: US12015411B2
- Status: Granted
- Kind: B2
- Application number: 17/752,774
- Filed: 2022-05-24
- Published: 2022-12-01
- Granted: 2024-06-18
- Earliest claimed: 2021-05-25
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Emil Gizdarski; Anubhav Sinha
- Web page: https://patentgrep.com/patent/US12015411B2

## CPC

- H03K 5/131: Digitally controlled
- G04F 10/005: {Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60)}
- H03K 2005/00058: {controlled by a digital setting}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G04F: TIME-INTERVAL MEASURING (measuring pulse characteristics G01R, e.g. G01R29/02; in radar or like systems G01S)

## Abstract

A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of the second multiplexer.

## Claims

### Claim 1

A delay selector, comprising:
a first multiplexer having a first input coupled to an input of the delay selector;
a first inverter coupled between the input of the delay selector and a second input of the first multiplexer;
a second multiplexer having a first input coupled to an output of the first multiplexer; and
a second inverter coupled between the output of the first multiplexer and a second input of the second multiplexer.

### Claim 2 (depends on 1)

The delay selector of claim 1, further comprising a buffer coupled between the output of the first multiplexer and the second input of the second multiplexer in series with the second inverter.

### Claim 3 (depends on 1)

The delay selector of claim 1, further comprising:
a third multiplexer having a first input coupled to an output of the second multiplexer;
a third inverter coupled between the output of the second multiplexer and a second input of the third multiplexer; and
one or more buffers coupled between the output of the second multiplexer and the second input of the third multiplexer in series with the third inverter.

### Claim 4 (depends on 3)

The delay selector of claim 3, wherein more buffers are coupled in series with the third inverter between the output of the second multiplexer and the second input of the third multiplexer than in series with the second inverter between the output of the first multiplexer and the second input of the second multiplexer.

### Claim 5 (depends on 1)

The delay selector of claim 1, further comprising a buffer coupled between an output of the second multiplexer and a first output of the delay selector, wherein the output of the second multiplexer is coupled to a second output of the delay selector.

### Claim 6

A time-to-digital converter (TDC) comprising:
a delay selector comprising:
a first multiplexer having a first input coupled to an input of the delay selector;
a first inverter coupled between the input of the delay selector and a second input of the first multiplexer;
a second multiplexer having a first input coupled to an output of the first multiplexer; and
a second inverter coupled between the output of the first multiplexer and a second input of the second multiplexer; and
a first flip flop having an input coupled to an output of the delay selector.

### Claim 7 (depends on 6)

The TDC of claim 6, further comprising:
a second flip flop; and
a buffer coupled between the output of the second multiplexer and an input of the second flip flop.

### Claim 8 (depends on 6)

The TDC of claim 6, further comprising:
a third multiplexer having a first input coupled to an output of the second multiplexer;
a third inverter coupled between the output of the second multiplexer and a second input of the third multiplexer; and
one or more buffers coupled between the output of the second multiplexer and the second input of the third multiplexer in series with the third inverter.

### Claim 9 (depends on 8)

The TDC of claim 8, wherein more buffers are coupled in series with the third inverter between the output of the second multiplexer and the second input of the third multiplexer than in series with the second inverter between the output of the first multiplexer and the second input of the second multiplexer.

### Claim 10 (depends on 8)

The TDC of claim 8, further comprising a register arranged to provide control signals to the first multiplexer and the second multiplexer.

### Claim 11 (depends on 10)

The TDC of claim 10, wherein the control signals adjust a delay provided by the delay selector.

### Claim 12

A TDC comprising:
a delay selector comprising:
a first multiplexer having a first input coupled to an input of the delay selector;
a first inverter coupled between the input of the delay selector and a second input of the first multiplexer;
a second multiplexer having a first input coupled to an output of the first multiplexer; and
a second inverter coupled between the output of the first multiplexer and a second input of the second multiplexer;
a third multiplexer arranged to receive an output of the delay selector at a first input of the third multiplexer; and
a first flip flop coupled to an output of the third multiplexer.

### Claim 13 (depends on 12)

The TDC of claim 12, further comprising:
a third inverter coupled between the output of the delay selector and a second input of the third multiplexer; and
a buffer coupled between the output of the delay selector and the first input of the third multiplexer.

### Claim 14 (depends on 12)

The TDC of claim 12, wherein a second input of the third multiplexer is an inverting input and is coupled to the output of the delay selector.

### Claim 15 (depends on 14)

The TDC of claim 14 wherein:
the second input of the first multiplexer is an inverting input comprising the first inverter; and
the second input of the second multiplexer is an inverting input comprising the second inverter.

### Claim 16 (depends on 12)

The TDC of claim 12, further comprising a register arranged to provide control signals to the first multiplexer and the second multiplexer.

### Claim 17 (depends on 16)

The TDC of claim 16, wherein the control signals adjust a delay provided by the delay selector.

### Claim 18 (depends on 16)

The TDC of claim 16, further comprising logic arranged to produce, to the third multiplexer, a control signal based on the control signals provided by the register.

### Claim 19 (depends on 18)

The TDC of claim 18, wherein the control signal produced by the logic is an exclusive or of the control signals provided by the register.

### Claim 20 (depends on 16)

The TDC of claim 16, wherein the register is further arranged to produce a control signal to the third multiplexer.