# US 12,015,410 B2 · Semiconductor device with daisy-chained delay cells and method of forming same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,015,410 B2
- Document ID: US12015410B2
- Status: Granted
- Kind: B2
- Application number: 17/822,559
- Filed: 2022-08-26
- Published: 2024-02-15
- Granted: 2024-06-18
- Earliest claimed: 2022-08-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc Nanjing Company, Limited
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc Nanjing Company, Limited
- Inventors: Huaixin Xian; Longbiao Lei; Sinpei Goa; Zhang-Ying Yan; Qingchao Meng; Jerry Chang Jui Kao
- Web page: https://patentgrep.com/patent/US12015410B2

## CPC

- H03K 3/86: Generating pulses by means of delay lines and not covered by the preceding subgroups
- H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)}
- H03K 3/356113: {using additional transistors in the input circuit}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A semiconductor device includes a first dummy group having a first set of dummy transistors; a first delay cell having a first set of active transistors; a second delay cell having a second set of active transistors; a second dummy group having a second set of dummy transistors; and relative to a first direction the first and second dummy groups and the first and second delay cells being arranged in a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and the first and second delay cells being free from having another dummy group therebetween.

## Claims

### Claim 1

A semiconductor device, comprising:
a first dummy group that includes a first set of dummy transistors;
a first delay cell that includes a first set of active transistors;
a second delay cell that includes a second set of active transistors;
a second dummy group that includes a second set of dummy transistors; and
relative to a first direction:
the first and second dummy groups and the first and second delay cells being arranged in a first row, the first row having a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and
the first and second delay cells being free from having another dummy group therebetween,
wherein the first delay cell includes:
a basic inverter configured to receive an input signal at a first node and output a first inverted signal at a second node, the first node representing an input node of the basic inverter; and
a float-resistant inverter configured to receive the first inverted signal at the second node and output a second inverted signal at a third node.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
the first sequence is open;
the semiconductor device further comprises:
a batch of N delay cells that correspondingly include N sets of active transistors, where N is a positive integer;
the batch of N delay cells is in the first row; and
relative to the first direction:
the first sequence of the first row is further arranged as the first dummy group, the first delay cell, the batch of N delay cells, the second delay cell, and the second dummy group; and
any two of the first and second delay cells and delay cells of the batch of N delay cells being free from having another dummy group being therebetween.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein each delay cell of the batch of N delay cells includes:
a first float-resistant inverter configured to receive an input signal at a first node and output a first inverted signal at a second node, the first node representing an input node of the first float-resistant inverter; and
a second float-resistant inverter configured to receive the first inverted signal at the second node and output a second inverted signal at a third node.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second delay cell includes:
a float-resistant inverter configured to receive an input signal at a first node and output a first inverted signal at a second node; and
a basic inverter configured to receive the first inverted signal and output a second inverted signal at a third node, where the second inverted signal is a delayed output.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a third dummy group that includes a third set of dummy transistors; and
a fourth dummy group that includes a fourth set of dummy transistors; and
the third and fourth dummy groups being arranged in a second row that extends in the first direction;
relative to the first direction, the third and fourth dummy groups being free from another dummy group or delay cell being therebetween; and
relative to a second direction perpendicular to the first direction, the second row abutting the first row.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising:
a third delay cell that includes a third set of active transistors; and
a fourth delay cell that includes a fourth set of active transistors; and
relative to the first direction:
the third delay cell and the fourth delay cell being arranged in the second row, the second row having a sequence arranged as the third dummy group, the third delay cell, the fourth delay cell and the fourth dummy group; and
the third and fourth delay cells being free from having another delay cell therebetween.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a third delay cell that includes one or more active transistors of a first conductivity-type and one or more active transistors of a second conductivity-type different than the first conductivity-type,
the one or more active transistors of the first conductivity-type being included in a second row,
the one or more active transistors of the second conductivity-type being included in a third row, and
the second and third rows being on opposite sides of the first row.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a third dummy group that includes a third set of dummy transistors;
a fourth dummy group that includes a fourth set of dummy transistors,
the third and fourth dummy groups being in a second row that extends in the first direction; and
relative to a second direction perpendicular to the first direction:
the second row abutting the first row;
the first dummy group overlapping the third dummy group; and
the second dummy group overlapping the fourth dummy group.

### Claim 9

A semiconductor device, comprising:
a first dummy group that includes a first set of dummy transistors;
a first delay cell that includes a first set of active transistors;
a second delay cell that includes a second set of active transistors;
a second dummy group that includes a second set of dummy transistors;
the first and second dummy groups and the first and second delay cells being arranged in a first row that extends in a first direction;
relative to the first direction:
the first row having a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and
the first and second delay cells being free from another dummy group therebetween;
a third dummy group that includes a third set of dummy transistors;
a first portion of a third delay cell that includes a third set of active transistors of a first conductivity-type;
a first portion of a fourth delay cell that includes a fourth set of active transistors of the first conductivity-type;
a fourth dummy group that includes a fourth set of dummy transistors;
relative to the first direction:
first portions of the third and fourth dummy groups and the first portions of the third and fourth delay cells being arranged in a first layer of a second row; and
the second row having a second sequence arranged as the third dummy group, the first portion of the third delay cell, the first portion of the fourth delay cell, and the fourth dummy group;
the third and fourth delay cells being free from another dummy group therebetween;
second portions of the third and fourth dummy groups being arranged in a second layer of the second row; and
relative to a second direction perpendicular to the first direction, the second row abutting the first row.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising:
a fifth dummy group that includes a fifth set of dummy transistors;
a second portion of the third delay cell that includes a fifth set of active transistors of a second conductivity-type different than the first conductivity-type;
a second portion of the fourth delay cell that includes a sixth set of active transistors of the second conductivity-type; and
a sixth dummy group that includes a sixth set of dummy transistors;
relative to the first direction:
the fifth and sixth dummy groups and the second portions of the third and fourth delay cells being arranged in a third row;
the third row having a third sequence arranged as the fifth dummy group, the second portion of the third delay cell, the second portion of the fourth delay cell, and the sixth dummy group; and
the third row being free from another dummy group being between the second portions of the third and fourth delay cells; and
relative to the second direction:
the third row abutting the first row; and
the second and third rows being on opposite sides of the first row.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein:
the first sequence is open;
the semiconductor device further comprises:
a batch of N delay cells that correspondingly include N sets of active transistors, where N is a positive integer;
the batch of N delay cells is in the first row; and
relative to the first direction:
the first row is arranged in a sequence arranged as the first dummy group, the first delay cell, the batch of N delay cells, the second delay cell, and the second dummy group; and
any two of the first and second delay cells and delay cells of the batch of N delay cells are free from having another dummy group being therebetween.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein each delay cell of the batch of N delay cells includes:
a first float-resistant inverter configured to receive an input signal at a first node and output a first inverted signal at a second node, the first node representing an input node of the first float-resistant inverter; and
a second float-resistant inverter configured to receive the first inverted signal and output a second inverted signal at a third node.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein:
the third row includes first and second layers that extend in the first direction; and
relative to the second direction:
the first layer of the third row includes a first portion of the third dummy group, a first portion of the fourth dummy group, a first portion of the fifth dummy group and a first portion of the sixth dummy group;
the second layer of the third row includes a second portion of the third dummy group and a second portion of the fourth dummy group but is free from another dummy group or delay cell between the second portions of the third and fourth dummy groups; and
the first layer of the third row abuts the first row.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the first delay cell includes:
a basic inverter configured to receive an input signal at a first node and output a first inverted signal at a second node, the first node representing an input node of the basic inverter; and
a float-resistant inverter configured to receive the first inverted signal and output a second inverted signal at a third node.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, wherein the second delay cell includes:
a float-resistant inverter to receive an input signal at a first node and output a first inverted signal at a second node; and
a basic inverter configured to receive the first inverted signal and output a second inverted signal at a third node, where the second inverted signal is a delayed output.

### Claim 16 (depends on 9)

The semiconductor device of claim 9, wherein:
the first and second layers extend in the first direction; and
the second layer is free from another dummy group or delay cell between the second portions of the first and second dummy groups; and
the first layer of the second row abuts the first row.

### Claim 17

A semiconductor device, comprises:
a first dummy group defined by one or more corresponding dummy transistors;
a second dummy group defined by one or more corresponding dummy transistors;
a first delay cell defined by one or more corresponding active transistors;
a second delay cell defined by one or more corresponding active transistors;
a batch of N delay cells, where N is a positive integer, defined by a batch of N sets of active transistors;
relative to a first direction:
the first and second dummy groups and the first and second delay cells being in a first row that extends in the first direction, the first row having an open first sequence arranged as the first dummy group, the first delay cell, the batch of N delay cells, the second delay cell, and the second dummy group;
the batch of N delay cells is in the first row; and
the first and second delay cells being free from having another dummy group therebetween;
a third dummy group defined by one or more corresponding dummy transistors;
a fourth dummy group defined by one or more corresponding dummy transistors; and
relative to the first direction:
the third and fourth dummy groups being in a second row that extends in the first direction; and
relative to a second direction perpendicular to the first direction:
the second row abutting the first row;
the first dummy group overlapping the third dummy group; and
the second dummy group overlapping the fourth dummy group.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein:
any two of the first and second delay cells and delay cells of the batch of N delay cells is free from having another dummy group being therebetween, and
the third and fourth dummy groups are free of having another dummy group or delay cell therebetween.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, further comprises:
a third delay cell defined by one or more corresponding active transistors; and
a fourth delay cell defined by one or more corresponding active transistors;
the third and fourth delay cells are in the second row; and
relative to the first direction:
a second sequence arranged as the third dummy group, the third delay cell, the fourth delay cell, and the fourth dummy group included in the second row; and
the third delay cell and the fourth delay cell are free from having another dummy group therebetween.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, further comprises:
a first portion of a third delay cell defined by one or more corresponding active transistors of a first conductivity-type; and
a first portion of a fourth delay cell defined by one or more corresponding active transistors of the first conductivity-type;
first and second layers included in the second row extend in the first direction; and
relative to the second direction:
the first layer of the second row includes a first portion of the third dummy group, a first portion of the second dummy group, the first portion of the third delay cell and the first portion of the fourth delay cell;
the second layer of the second row includes a second portion of the first dummy group and a second portion of the second dummy group but is free from another dummy group or delay cell being between the second portions of the first and second dummy groups; and
the first layer of the second row abuts the first row.