# US 12,015,409 B2 · Flip-flop with delineated layout for reduced footprint

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- Number: US 12,015,409 B2
- Document ID: US12015409B2
- Status: Granted
- Kind: B2
- Application number: 17/339,121
- Filed: 2021-06-04
- Published: 2021-09-23
- Granted: 2024-06-18
- Earliest claimed: 2016-05-02
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chi-Lin Liu; Ting-Wei Chiang; Jerry Chang-Jui Kao; Hui-Zhong Zhuang; Lee-Chung Lu; Shang-Chih Hsieh; Che Min Huang
- Web page: https://patentgrep.com/patent/US12015409B2

## CPC

- H03K 3/35625: {using complementary field-effect transistors}
- G01R 31/318541: {Scan latches or cell details}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 89/10: Integrated device layouts
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including a first region and a second region that is adjacent in a first direction to the first region; and
a first gate electrode, a second gate electrode, and a third gate electrode that extend from the first region toward the second region,
wherein each of the first and second regions includes a P-type metal-oxide field-effect transistor (PMOSFET) region and an N-type metal-oxide field-effect transistor (NMOSFET) region that is adjacent in the first direction to the PMOSFET,
wherein each of the first, second, and third gate electrodes extends in the first direction such that each of the first, second, and third gate electrodes extends lengthwise in the first direction,
wherein each of the PMOSFET region and the NMOSFET region extends lengthwise in a second direction different from the first direction,
wherein the second gate electrode is interposed between the first gate electrode and the third gate electrode in the second direction,
wherein the second gate electrode extends continuously from the PMOSFET region in the first region to the NMOSFET region in the second region, and
wherein the first gate electrode includes a first gate of the first region and a first gate of the second region, the first gate of the first region and the first gate of the second region being aligned and connected with each other in the first direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a length of the second gate electrode is substantially equal to a sum of lengths of the first gate electrode and the third gate electrode.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first direction is perpendicular to the second direction.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising: a gate contact electrically connected to the second gate electrode, wherein the second gate electrode includes a second gate of the first region and a second gate of the second region, the second gate of the first region and the second gate of the second region being aligned and connected with each other in the first direction.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the second gate of the first and second regions includes a gate of a PMOS transistor of the first region, a gate of an NMOS transistor of the first region, a gate of an NMOS transistor of the second region, and a gate of a PMOS transistor of the second region.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the third gate electrode includes a third gate of the first region and a third gate of the second region, wherein the third gate of the first region and the third gate of the second region are spaced apart from each other in the first direction.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first gate electrode has a straight line shape.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the second gate electrode has a straight line shape.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first region includes a master latch of a flip-flop cell, and the second region includes a slave latch of the flip-flop cell.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the second gate electrode has a length longer than a length of the first gate electrode when measured along the first direction.

### Claim 11

A semiconductor device, comprising:
a flip-flop cell on a substrate, the flip-flop cell including a first region including a master latch and a second region including a slave latch, the second region being adjacent in a first direction to the first region; and
a first gate electrode, a second gate electrode, and a third gate electrode that extend from the first region toward the second region and are sequentially arranged in a second direction different from the first direction,
wherein each of the first, second, and third gate electrodes extends in the first direction, and wherein the second gate electrode extends continuously through a gate of a PMOS transistor of the first region, to a gate of an NMOS transistor of the first region, to a gate of an NMOS transistor of the second region, and to a gate of a PMOS transistor of the second region.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the master latch and the slave latch are adjacent to each other along the first direction.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the first gate electrode includes a gate of an NMOS transistor of the first region and a gate of an NMOS transistor of the second region.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the third gate electrode includes a third gate of the first region and a third gate of the second region, wherein the third gate of the first region includes a gate of a PMOS transistor of the first region and the third gate of the second region includes a gate of a PMOS transistor of the second region, and wherein the third gate of the first region and the third gate of the second region are spaced apart from each other in the first direction.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the first direction is perpendicular to the second direction.

### Claim 16

A semiconductor device, comprising:
a first flip-flop cell and a second flip-flop cell that are adjacent to each other in a first direction on a substrate; and
a first gate electrode, a second gate electrode, and a third gate electrode that extend from the first flip-flop cell toward the second flip-flop cell and are sequentially arranged in a second direction different from the first direction,
wherein each of the first, second, and third gate electrodes extends in the first direction,
wherein an end of the third gate electrode is laterally spaced from an end of the first gate electrode along the second direction, wherein the end of the third gate electrode is aligned with the end of the first gate electrode along the first direction, wherein the third gate electrode, starting from the end of the third gate electrode, extends away from the first gate electrode along the first direction, and
wherein the second gate electrode includes a gate of a PMOS transistor of the first flip-flop cell, a gate of an NMOS transistor of the first flip-flop cell, a gate of an NMOS transistor of the second flip-flop cell, and a gate of a PMOS transistor of the second flip-flop cell.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the second gate electrode extends continuously through the gate of the PMOS transistor of the first flip-flop cell, the gate of the NMOS transistor of the first flip-flop cell, the gate of the NMOS transistor of the second flip-flop cell, and the gate of the PMOS transistor of the second flip-flop cell.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the first gate electrode includes a first gate that is a gate of an NMOS transistor of the first flip-flop cell and a gate of an NMOS transistor of the second flip-flop cell.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the third gate electrode includes a third gate of the first flip-flop cell that is a gate of a PMOS transistor of the first flip-flop cell and a third gate of the second flip-flop cell that is a gate of a PMOS transistor of the second flip-flop cell, wherein the third gate of the first flip-flop cell and the third gate of the second flip-flop cell are spaced apart from each other in the first direction.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the first direction is perpendicular to the second direction.