# US 12,015,405 B2 · IC with first and second functional circuits coupling only first circuits to output bond pads > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,015,405 B2 - Document ID: US12015405B2 - Status: Granted - Kind: B2 - Application number: 17/576,376 - Filed: 2022-01-14 - Published: 2022-05-05 - Granted: 2024-06-18 - Earliest claimed: 2017-06-28 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: H. Pooya Forghani-zadeh; George Vincent Konnail; Christopher Adam Opoczynski - Web page: https://patentgrep.com/patent/US12015405B2 ## CPC - H03K 19/1776: for memories - H03K 19/017509: {Interface arrangements} - H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A family of digital logic functions has the same specifications for input and output voltages and the same number of bond pads. A digital logic integrated circuit for the family includes a substrate of semiconductor material having a core area and a peripheral area; a certain number of bond pads formed in the peripheral area, the certain number of bond pads determining the total area of the substrate; programmable digital logic transistor circuitry formed in the core area for each of the digital logic functions in the family; programmable input and output circuitry formed in the peripheral area; programming circuitry for programming the programmable digital logic transistor circuitry into a selected digital logic function; and programmable input and output means for programming the input and output circuitry into input and output circuits for the selected digital logic function. ## Claims ### Claim 1 An integrated circuit comprising: (a) a substrate of semiconductor material having a core area and a peripheral area; (b) bond pads formed in the peripheral area, the bond pads including first and second input bond pads and an output bond pad; (c) a first set of one or more programmable digital logic transistor circuits formed in the core area, each programmable digital logic transistor circuit of the first set having a first programmable function, each programmable digital logic transistor circuit of the first set having respective first and second inputs coupled to the first and second input bond pads respectively, and having a respective output coupled to the output bond pad; (d) a second set of one or more programmable digital logic transistor circuits formed in the core area, each programmable digital logic transistor circuit of the second set having a second programmable function different than the first programmable function, each functional programmable digital logic transistor circuit of the second set having respective first and second inputs and having a respective output; (e) conductive material coupling the first and second input bond pads to the respective first and second inputs of the one or more programmable digital logic transistor circuits of the first set and coupling the output bond pad only to the respective output of the one or more programmable digital logic transistor circuits of the first set; and (f) control circuitry for programming the first set of one or more programmable digital logic transistor circuits and the second set of one or more programmable digital logic transistor circuits. ### Claim 2 (depends on 1) The integrated circuit of claim 1 in which the conductive material includes a strap. ### Claim 3 (depends on 1) The integrated circuit of claim 1 in which the conductive material includes a fuse. ### Claim 4 (depends on 1) The integrated circuit of claim 1 in which the conductive material includes metal. ### Claim 5 (depends on 1) The integrated circuit of claim 1 in which the conductive material includes an upper level metal. ### Claim 6 (depends on 1) The integrated circuit of claim 1 in which the first set of programmable digital logic transistor circuits includes one or more AND gates. ### Claim 7 (depends on 1) The integrated circuit of claim 1 in which the first set of programmable digital logic transistor circuits includes one or more OR gates. ### Claim 8 (depends on 1) The integrated circuit of claim 1 in which the first set of programmable digital logic transistor circuits includes one or more NAND gates. ### Claim 9 (depends on 1) The integrated circuit of claim 1 in which the first set of programmable digital logic transistor circuits includes one or more NOR gates. ### Claim 10 (depends on 1) The integrated circuit of claim 1 in which the second set of programmable digital logic transistor circuits includes one or more AND gates. ### Claim 11 (depends on 1) The integrated circuit of claim 1 in which the second set of programmable digital logic transistor circuits includes one or more OR gates. ### Claim 12 (depends on 1) The integrated circuit of claim 1 in which the second set of programmable digital logic transistor circuits includes one or more NAND gates. ### Claim 13 (depends on 1) The integrated circuit of claim 1 in which the second set of programmable digital logic transistor circuits includes one or more NOR gates. ### Claim 14 (depends on 1) The integrated circuit of claim 1 in which the conductive material includes multiplexer circuits coupling the output bond pad to the respective output of the one or more programmable digital logic transistor circuits of the first set. ### Claim 15 (depends on 1) The integrated circuit of claim 1 in which the conductive material couples the first and second input bond pads to the respective first and second inputs of the one or more programmable digital logic transistor circuits of the second set. ### Claim 16 (depends on 1) The integrated circuit of claim 1 including a third set of one or more programmable digital logic transistor circuits formed in the core area, each programmable digital logic transistor circuit of the third set having a third programmable function different from the first and second programmable functions, each programmable digital logic transistor circuit of the third set having respective first and second inputs coupled to the first and second input bond pads, and having a respective output. ### Claim 17 (depends on 1) The integrated circuit of claim 1 including: a third set of programmable digital logic transistor circuits formed in the core area, each programmable digital logic transistor circuit of the third set having a programmable third function different from the first and second programmable functions, each programmable functional circuit of the third set having respective first and second inputs coupled to the first and second input bond pads, and having a respective output; and a fourth set of programmable digital logic transistor circuits formed in the core area, each programmable digital logic transistor circuit of the fourth set having a programmable fourth function different from the first, second, and third programmable functions, each programmable digital logic transistor circuit of the fourth set having respective first and second inputs coupled to the first and second input bond pads, and having a respective output. ### Claim 18 (depends on 1) The integrated circuit of claim 1 wherein the controller includes a non-volatile memory for supplying control signals for programming the first and second sets of programmable digital logic transistor circuitry.