# US 12,015,404 B2 · Logic process-based level conversion circuit of flash field programmable gate array (FPGA)

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- Number: US 12,015,404 B2
- Document ID: US12015404B2
- Status: Granted
- Kind: B2
- Application number: 17/940,001
- Filed: 2022-09-08
- Published: 2023-01-05
- Granted: 2024-06-18
- Earliest claimed: 2021-12-22
- Assignees: Wuxi Esiontech Co., Ltd.
- Applicants: Wuxi Esiontech Co., Ltd.
- Inventors: Zhengzhou Cao; Yueer Shan; Zhenkai Ji; Jing Sun; Chunyan He; Guangming Li
- Web page: https://patentgrep.com/patent/US12015404B2

## CPC

- H03K 19/1733: {Controllable logic circuits (H03K19/177 takes precedence)}
- H03K 19/17704: the logic functions being realised by the interconnection of rows and columns
- H03K 19/17748: Structural details of configuration resources
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A logic process-based level conversion circuit of a flash flash field programmable gate array (FPGA) performs three-stage level conversion by using three conversion modules. A first-stage conversion module is configured to convert an input first signal of a VDD-GND voltage domain into a second signal of a VP1-GND voltage domain, an intermediate-stage conversion module is configured to convert the input second signal of the VP1-GND voltage domain into a third signal of a VP1-VN voltage domain, and a drive-stage conversion module is configured to convert the input third signal of the VP1-VN voltage domain into a drive signal of a VP2-VN voltage domain and output a drive word line. The logic process-based level conversion circuit reduces the pressure of conversion at each stage, ensures a capability of driving the next stage, increases the conversion speed, and provides a large driving capability at the last stage.

## Claims

### Claim 1

A logic process-based level conversion circuit of a flash field programmable gate array (FPGA) comprising a first-stage conversion module, an intermediate-stage conversion module, and a drive-stage conversion module, wherein the first-stage conversion module, the intermediate-stage conversion module, and the drive-stage conversion module are successively cascaded, wherein
the first-stage conversion module is configured to convert an input first signal of a VDD-GND voltage domain into a second signal of a VP1-GND voltage domain and output the second signal to the intermediate-stage conversion module; the intermediate-stage conversion module is configured to convert the input second signal of the VP1-GND voltage domain into a third signal of a VP1-VN voltage domain and output the third signal to the drive-stage conversion module; and the drive-stage conversion module is configured to convert the input third signal of the VP1-VN voltage domain into a drive signal of a VP2-VN voltage domain and output a word line for driving the flash FPGA; and
a logic process is controlled to output a corresponding voltage combination to complete an erasure operation or a programming operation on the flash FPGA, wherein the voltage combination comprises a core low voltage VDD, an intermediate voltage VP1, a drive-stage voltage VP2, and a negative voltage VN, wherein the core low voltage VDD, the intermediate voltage VP1, the drive-stage voltage VP2, and the negative voltage VN are provided by the logic process, wherein GND is a grounding voltage and VP2≥VP1≥VDD.

### Claim 2 (depends on 1)

The logic process-based level conversion circuit according to claim 1, wherein when the programming operation is performed on the flash FPGA, a voltage value of the core low voltage VDD, a voltage value of the intermediate voltage VP1, and a voltage value of the drive-stage voltage VP2 provided by the logic process are controlled to increase successively, the voltage value of the drive-stage voltage VP2 is a positive high voltage HV required for programming a flash cell, and the drive signal of the VP2-VN voltage domain output by the drive-stage conversion module controls the word line to apply the positive high voltage HV to a gate terminal of the flash cell to complete the programming operation.

### Claim 3 (depends on 1)

The logic process-based level conversion circuit according to claim 1, wherein when the erasure operation is performed on the flash FPGA, voltage values of the intermediate voltage VP1, the drive-stage voltage VP2, and the core low voltage VDD provided by the logic process are controlled to be equal, the negative voltage VN provided by the logic process is controlled to be a negative high voltage LV required for erasing a flash cell, and the drive signal of the VP2-VN voltage domain output by the drive-stage conversion module controls the word line to apply the negative high voltage LV to a gate terminal of the flash cell to complete the erasure operation.

### Claim 4 (depends on 1)

The logic process-based level conversion circuit according to claim 1, wherein each of the intermediate-stage conversion module and the drive-stage conversion module is provided with voltage dividing switch transistors for voltage division, and the voltage dividing switch transistors of each of the intermediate-stage conversion module and the drive-stage conversion module are controlled by a gate voltage control signal, wherein voltage values of the gate voltage control signal are different in different time periods of a working cycle of the logic process-based level conversion circuit to adjust states of the voltage dividing switch transistors and reduce a working time of a device in the logic process-based level conversion circuit under a break-down voltage.

### Claim 5 (depends on 4)

The logic process-based level conversion circuit according to claim 4, wherein the second signal and the third signal are differential signals;
wherein in the intermediate-stage conversion module:
sources of a positive channel metal oxide semiconductor (PMOS) transistor P3, a PMOS transistor P4, a PMOS transistor P5, and a PMOS transistor P6 are connected to each other and to the intermediate voltage VP1; a drain of the PMOS transistor P4 is connected to a drain of a negative channel metal oxide semiconductor (NMOS) transistor N3, and a source of the NMOS transistor N3 is connected to a drain of an NMOS transistor N5; a drain of the PMOS transistor P5 is connected to a drain of an NMOS transistor N4, and a source of the NMOS transistor N4 is connected to a drain of an NMOS transistor N6; a source of the NMOS transistor N5 and a source of the NMOS transistor N6 are connected to each other and to the negative voltage VN; a drain of the PMOS transistor P3, a gate of the PMOS transistor P4, the drain of the PMOS transistor P5, and a gate of the NMOS transistor N5 are connected; a drain of the PMOS transistor P6, a gate of the PMOS transistor P5, the drain of the PMOS transistor P4, and a gate of the NMOS transistor N6 are connected; a gate of the PMOS transistor P3 and a gate of the PMOS transistor P6 are configured as a first differential pair for obtaining the second signal; the gate of the NMOS transistor N5 and the gate of the NMOS transistor N6 are configured as a second differential pair for outputting the third signal; the NMOS transistor N3 and the NMOS transistor N4 are configured as the voltage dividing switch transistors in the intermediate-stage conversion module; and a gate of the NMOS transistor N3 and a gate of the NMOS transistor N4 are connected and controlled by the gate voltage control signal.

### Claim 6 (depends on 5)

The logic process-based level conversion circuit according to claim 5, wherein in any working cycle of performing the programming operation or the erasure operation on the flash FPGA, the working cycle successively comprises a level conversion phase and a maintenance phase, wherein the level conversion phase is used to complete signal conversion in different voltage domains, and the maintenance phase is used to maintain a signal state;
in the maintenance phase of the working cycle, the voltage value of the gate voltage control signal is the negative voltage VN, the voltage dividing switch transistors N3 and N4 in the intermediate-stage conversion module are turned off, the voltage dividing switch transistors N7 and N8 in the drive-stage conversion module are turned off, a state of the logic process-based level conversion circuit is maintained by voltages of parasitic capacitors of the logic process-based level conversion circuit and the logic process-based level conversion circuit is not driven in a pull-down manner; charges on the parasitic capacitors enable data to be retained, but a voltage difference formed by the charges on the parasitic capacitors is less than the break-down voltage of the device to protect the PMOS transistor P3, the PMOS transistor P4, the PMOS transistor P5, and the PMOS transistor P6 in the intermediate-stage conversion module and the PMOS transistor P7 and the PMOS transistor P8 in the drive-stage conversion module; and
the intermediate-stage conversion module has a first parasitic capacitor between the PMOS transistor P4 and the NMOS transistor N3 and a second parasitic capacitor between the PMOS transistor P5 and the NMOS transistor N4, and the drive-stage conversion module has a third parasitic capacitor between the PMOS transistor P7 and the NMOS transistor N7 and a fourth parasitic capacitor between the PMOS transistor P8 and the NMOS transistor N8.

### Claim 7 (depends on 6)

The logic process-based level conversion circuit according to claim 6, wherein in any working cycle of performing the programming operation or the erasure operation on the flash FPGA, in the level conversion phase of the working cycle, the voltage value of the gate voltage control signal is equal to the intermediate voltage VP1; wherein when the programming operation is performed on the flash FPGA, the positive high voltage HV in the drive-stage conversion module is not transmitted to the NMOS transistor N9 and the NMOS transistor N10 due to clamping of the voltage dividing switch transistors N7 and N8, such that safety voltage tolerances of the NMOS transistor N7, the NMOS transistor N8, the NMOS transistor N9, and the NMOS transistor N10 are increased.

### Claim 8 (depends on 7)

The logic process-based level conversion circuit according to claim 7, wherein in any working cycle, a duration of the maintenance phase is greater than a duration of the level conversion phase.

### Claim 9 (depends on 4)

The logic process-based level conversion circuit according to claim 4, wherein the third signal and the drive signal are differential signals;
wherein in the drive-stage conversion module:
sources of a PMOS transistor P7 and a PMOS transistor P8 are connected to each other and to the drive-stage voltage VP2; a drain of the PMOS transistor P7 is connected to a gate of the PMOS transistor P8 and a drain of an NMOS transistor N7; a drain of the PMOS transistor P8 is connected to a gate of the PMOS transistor P7 and a drain of an NMOS transistor N8; a source of the NMOS transistor N7 is connected to a drain of an NMOS transistor N9; a source of the NMOS transistor N8 is connected to a drain of an NMOS transistor N10; a source of the NMOS transistor N9 and a source of the NMOS transistor N10 are connected to each other and to the negative voltage VN; a gate of the NMOS transistor N9 and a gate of the NMOS transistor N10 are configured as a first differential pair for obtaining the third signal; the drain of the NMOS transistor N7 and the drain of the NMOS transistor N8 are configured as a second differential pair for outputting the drive signal; the NMOS transistor N7 and the NMOS transistor N8 are configured as the voltage dividing switch transistors in the drive-stage conversion module; and a gate of the NMOS transistor N7 and a gate of the NMOS transistor N8 are connected and controlled by the gate voltage control signal.

### Claim 10 (depends on 9)

The logic process-based level conversion circuit according to claim 9, wherein in any working cycle of performing the programming operation or the erasure operation on the flash FPGA, the working cycle successively comprises a level conversion phase and a maintenance phase, wherein the level conversion phase is used to complete signal conversion in different voltage domains, and the maintenance phase is used to maintain a signal state;
in the maintenance phase of the working cycle, the voltage value of the gate voltage control signal is the negative voltage VN, the voltage dividing switch transistors N3 and N4 in the intermediate-stage conversion module are turned off, the voltage dividing switch transistors N7 and N8 in the drive-stage conversion module are turned off, a state of the logic process-based level conversion circuit is maintained by voltages of parasitic capacitors of the logic process-based level conversion circuit and the logic process-based level conversion circuit is not driven in a pull-down manner; charges on the parasitic capacitors enable data to be retained, but a voltage difference formed by the charges on the parasitic capacitors is less than the break-down voltage of the device to protect the PMOS transistor P3, the PMOS transistor P4, the PMOS transistor P5, and the PMOS transistor P6 in the intermediate-stage conversion module and the PMOS transistor P7 and the PMOS transistor P8 in the drive-stage conversion module; and
the intermediate-stage conversion module has a first parasitic capacitor between the PMOS transistor P4 and the NMOS transistor N3 and a second parasitic capacitor between the PMOS transistor P5 and the NMOS transistor N4, and the drive-stage conversion module has a third parasitic capacitor between the PMOS transistor P7 and the NMOS transistor N7 and a fourth parasitic capacitor between the PMOS transistor P8 and the NMOS transistor N8.

### Claim 11 (depends on 10)

The logic process-based level conversion circuit according to claim 10, wherein in any working cycle of performing the programming operation or the erasure operation on the flash FPGA, in the level conversion phase of the working cycle, the voltage value of the gate voltage control signal is equal to the intermediate voltage VP1; wherein when the programming operation is performed on the flash FPGA, the positive high voltage HV in the drive-stage conversion module is not transmitted to the NMOS transistor N9 and the NMOS transistor N10 due to clamping of the voltage dividing switch transistors N7 and N8, such that safety voltage tolerances of the NMOS transistor N7, the NMOS transistor N8, the NMOS transistor N9, and the NMOS transistor N10 are increased.

### Claim 12 (depends on 11)

The logic process-based level conversion circuit according to claim 11, wherein in any working cycle, a duration of the maintenance phase is greater than a duration of the level conversion phase.

### Claim 13 (depends on 1)

The logic process-based level conversion circuit according to claim 1, wherein the first signal is a single-ended signal, and the second signal is a differential signal; and in the first-stage conversion module, sources of a PMOS transistor P1 and a PMOS transistor P2 are connected to each other and to the intermediate voltage VP1, a drain of the PMOS transistor P1 is connected to a gate of the PMOS transistor P2 and a drain of an NMOS transistor N1, a drain of the PMOS transistor P2 is connected to a gate of the PMOS transistor P1 and a drain of an NMOS transistor N2, and a source of the NMOS transistor N1 and a source of the NMOS transistor N2 are connected to each other and to GND; and
a source of a PMOS transistor P0 is connected to the core low voltage VDD, a drain of the PMOS transistor P0 is connected to a drain of an NMOS transistor N0, a source of the NMOS transistor N0 is connected to GND, a gate of the PMOS transistor P0 and a gate of the NMOS transistor N0 are connected, the gate of the PMOS transistor P0 obtains the first signal, the gate of the NMOS transistor N0 obtains the first signal, the drain of the PMOS transistor P0 outputs an inverse signal of the first signal and is connected to a gate of the NMOS transistor N1, a gate of the NMOS transistor N2 is configured to obtain the first signal, and the drain of the PMOS transistor P1 and the drain of the PMOS transistor P2 are configured as a differential pair for outputting the second signal.