# US 12,015,403 B2 · Semiconductor apparatus performing a plurality of clock signaling operations and semiconductor system including the same

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- Number: US 12,015,403 B2
- Document ID: US12015403B2
- Status: Granted
- Kind: B2
- Application number: 18/084,240
- Filed: 2022-12-19
- Published: 2023-11-16
- Granted: 2024-06-18
- Earliest claimed: 2022-05-16
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Ji Hyo Kang; Kyung Hoon Kim
- Web page: https://patentgrep.com/patent/US12015403B2

## CPC

- H03K 19/018521: {of complementary type, e.g. CMOS}
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- H03K 17/6872: {using complementary field-effect transistors}
- G11C 7/1066: {Output synchronization}
- G11C 7/1093: {Input synchronization}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor apparatus includes a clock distribution network, a data output circuit, and a data input circuit. The clock distribution network receives a system clock signal and drives the system clock signal to a CMOS level and a CML level to signal in different manners. The data output circuit outputs data based on the clock signal driven to the CMOS level. The data input circuit receives data based on the clock signal driven to the CML level.

## Claims

### Claim 1

A semiconductor apparatus comprising:
a global dock tree configured to drive a system dock signal to a complementary metal oxide semiconductor (CMOS) level to generate a first distribution dock signal and configured to drive the system dock signal to a current mode logic (CML) level to generate a second distribution dock signal;
a data output circuit configured to output data based on the first distribution dock signal; and
a data input circuit configured to receive the data based on the second distribution clock signal.

### Claim 2 (depends on 1)

The semiconductor apparatus of claim 1, wherein the system clock signal is a signal swinging to a CML level.

### Claim 3 (depends on 1)

The semiconductor apparatus of claim 1, wherein the global clock tree includes:
a CML-CMOS converter configured to convert the system clock signal to a signal swinging to a CMOS level;
a CMOS driver configured to drive an output signal from the CML-CMOS converter to generate the first distribution clock signal; and
a CML driver configured to drive the system clock signal to a CML level to generate the second distribution clock signal.

### Claim 4 (depends on 1)

The semiconductor apparatus of claim 1, further comprising a local dock tree configured to receive the first distribution dock signal and the second distribution dock signal, configured to generate a data output dock signal from the first distribution dock signal, and configured to generate a data input dock signal from the second distribution dock signal, and
wherein the data output circuit is configured to output the data in synchronization with the data output clock signal, and the data input circuit is configured to receive the data in synchronization with the data input dock signal.

### Claim 5 (depends on 4)

The semiconductor apparatus of claim 4, wherein the local dock tree includes:
a first driver configured to drive the first distribution dock signal to generate the data output dock signal;
a CML-CMOS converter configured to convert the second distribution dock signal to a signal swinging to a CMOS level; and
a second driver configured to drive an output signal from the CML-CMOS converter to generate the data input dock signal.

### Claim 6 (depends on 1)

The semiconductor apparatus of claim 1, further comprising:
a local clock tree configured to generate a data output clock signal based on the first distribution clock signal; and
a read dock output circuit coupled to the local dock tree and configured to output the data output dock signal, and
wherein the data output dock signal, output from the read dock output circuit, is synchronized with the data that are output from the data output circuit.

### Claim 7

A semiconductor apparatus comprising:
a global clock tree configured to:
drive a system clock signal to a complementary metal oxide semiconductor (CMOS) level to generate a first distribution clock signal and transmit the first distribution clock signal through a first clock transmission line;
drive the system clock signal to a current mode logic (CML) level to generate a second distribution clock signal and transmit the second distribution clock signal through a second clock transmission line; and
a local clock tree configured to:
receive the first distribution clock signal through the first clock transmission line and generate a read clock signal based on the first distribution clock signal;
receive the second distribution clock signal through the second clock transmission line and generate a write clock signal based on the second distribution clock signal.

### Claim 8 (depends on 7)

The semiconductor apparatus of claim 7, wherein the system clock signal is a signal swinging to a CML level.

### Claim 9 (depends on 7)

The semiconductor apparatus of claim 7, wherein the global clock tree includes:
a CML-CMOS converter configured to convert the system dock signal to a signal swinging to a CMOS level;
a CMOS driver configured to drive an output signal from the CML-CMOS converter to generate the first distribution dock signal; and
a CML driver configured to drive the system dock signal to a CML level to generate the second distribution clock signal.

### Claim 10 (depends on 7)

The semiconductor apparatus of claim 7, wherein the local clock tree includes:
a first driver configured to drive the first distribution clock signal to generate the read clock signal;
a CML-CMOS converter configured to convert the second distribution clock signal to a signal swinging to a CMOS level; and
a second driver configured to drive an output signal from the CML-CMOS converter to generate the write clock signal.

### Claim 11 (depends on 7)

The semiconductor apparatus of claim 7, further comprising:
a data output circuit configured to output, in synchronization with the read clock signal, data to an external apparatus; and
a data input circuit configured to receive, in synchronization with the write clock signal, the data that are provided from the external apparatus.

### Claim 12 (depends on 11)

The semiconductor apparatus of claim 11, further comprising a read dock output circuit configured to transmit the read dock signal to the external apparatus,
wherein the read clock signal that is output from the read dock output circuit is synchronized with the data that are output from the data output circuit.

### Claim 13

A semiconductor apparatus comprising:
a global dock tree configured to:
receive a system clock signal and generate a first distribution dock signal during a read operation of the semiconductor apparatus; and
generate a second distribution dock signal during a write operation of the semiconductor apparatus, the second distribution dock signal swinging within a smaller range than the first distribution clock signal; and
a local clock tree configured to generate a data output dock signal from the first distribution dock signal during the read operation and configured to generate a data input clock signal from the second distribution dock signal during the write operation.

### Claim 14 (depends on 13)

The semiconductor apparatus of claim 13, wherein the system clock signal is a signal swinging to a current mode logic (CML) level.

### Claim 15 (depends on 13)

The semiconductor apparatus of claim 13, wherein the global clock tree includes:
a CML-CMOS converter configured to convert the system dock signal to a signal swinging to a complementary metal oxide semiconductor (CMOS) level;
a CMOS driver configured to drive, based on a first enable signal, an output signal from the CML-CMOS converter to generate the first distribution clock signal; and
a CML driver configured to drive, based on a second enable signal, the system clock signal to a CML level to generate the second distribution clock signal.

### Claim 16 (depends on 13)

The semiconductor apparatus of claim 13, wherein the local clock tree includes:
a first driver configured to drive the first distribution clock signal to generate the data output clock signal;
a CML-CMOS converter configured to convert the second distribution clock signal to a signal swinging to a CMOS level; and
a second driver configured to drive an output signal from the CML-CMOS converter to generate the data input clock signal.

### Claim 17 (depends on 13)

The semiconductor apparatus of claim 13, further comprising:
a data output circuit configured to output, based on the data output dock signal, data to an external apparatus; and
a data input circuit configured to receive, based on the data input dock signal, data that are provided from the external apparatus.

### Claim 18 (depends on 17)

The semiconductor apparatus of claim 17, wherein the local clock tree is configured to output the data output clock signal as a strobe signal to the external apparatus.