# US 12,015,210 B2 · Phased antenna array device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,015,210 B2 - Document ID: US12015210B2 - Status: Granted - Kind: B2 - Application number: 16/979,805 - Filed: 2019-03-12 - Published: 2021-02-25 - Granted: 2024-06-18 - Earliest claimed: 2018-03-12 - Assignees: TTP Plc - Applicants: Ttp PLC - Inventors: Vlad Lenive - Web page: https://patentgrep.com/patent/US12015210B2 ## CPC - H01Q 3/42: using frequency-mixing {(H01Q3/2676 takes precedence)} - H01Q 3/46: Active lenses or reflecting arrays - H01Q 1/523: {between antennas of an array} - H01Q 3/36: with variable phase-shifters - H01Q 5/50: Feeding or matching arrangements for broad-band or multi-band operation - H01Q 21/0018: {Space- fed arrays} - H01Q 23/00: Antennas with active circuits or circuit elements integrated within them or attached to them - H04B 1/0064: {with separate antennas for the more than one band (H04B1/0053 takes precedence)} - H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72) - H04B: TRANSMISSION ## Abstract A phased antenna array device comprises at least one input port for interfacing receive and transmit RF signals to/from an antenna array. A feeding line is provided to carry RF signals of two orthogonal polarizations from the input port P1, and at least one antenna feed element with an aperture or cross section having an order of symmetry C4 and supporting RF signals of two orthogonal polarizations is provided. At least one first substrate contains a plurality of antenna elements integrated into the substrate, with each antenna element capable of operating at two orthogonal polarizations. A plurality of phase shifters are connected to corresponding antenna elements, each phase shifter operating at two orthogonal polarizations, the output port of each phase shifter being connected to a short circuit. ## Claims ### Claim 1 A phased antenna array device comprising: at least one input port P1 for interfacing receive and transmit RF signals to/from an antenna array; at least one feeding line designed to carry RF signals of two orthogonal polarizations from the at least one input port P1; at least one antenna feed element with an aperture or cross section having an order of symmetry C4 and supporting RF signals of two orthogonal polarizations; at least one first substrate from one or more substrates containing a plurality of antenna elements integrated into the at least one first substrate, with each antenna element capable of operating at two orthogonal polarizations; diplexer junctions integrated into the at least one first substrate, with each diplexer junction operating at two orthogonal polarizations, wherein at least one of the plurality of antenna elements are connected to the diplexer junctions; a plurality of phase shifters connected to corresponding antenna elements, each phase shifter operating at two orthogonal polarizations, an output port of each phase shifter being connected to a short circuit, wherein respective ones of the plurality of phase shifters (PS1-PS1(?)) are connected to corresponding transmission ports of the diplexer junctions; a plurality of orthomode transducers (OMTs) connected to corresponding output receive ports of the diplexer junctions (D1-Dn) with each OMT performing separation of orthogonally polarized signals inside a receive frequency band; and a first plurality of RF IC chips (D1-Dj) each containing an LNA, PLL frequency synthesizer and downconverter connected to corresponding receive output ports of each OMT, with each IC chip performing RF processing inside the receive frequency band, including amplification and down-conversion, for each of the two orthogonal polarizations separated by the OMT in use, the output port of each IC chip being connected to a corresponding combiner, wherein, in use, a first receive beam is formed using plurality of synchronization signals fed into the one or more substrates via a synchronization bus Bs and connected to the synchronization inputs of the PLL frequency synthesizers via switches (S11-S1j) so as to allow a selection of the relative phase of the LO signal generated by each PLL. ### Claim 2 (depends on 1) The phased antenna array device according to claim 1, further comprising: a numerically controlled oscillator (NCO) providing a plurality of synchronization signals of all required phase states for the phased antenna array device as well as phase and frequency stability locked to a single Xtal-stabilized reference. ### Claim 3 (depends on 1) The phased antenna array device according to claim 1, further comprising: a second plurality of RF IC chips with their corresponding inputs connected parallel to the corresponding inputs of the first plurality of RF IC chips and having outputs connected to a second set of combiners, forming a second receive beam, independent from the first receive beam, with a second set of switches providing, in use, independent scanning/beamforming for the second receive beam. ### Claim 4 (depends on 1) The phased antenna array device according to claim 1, further comprising: a first superstrate positioned over the one or more substrates and arranged to correct phase distribution of the signals radiated by the one or more substrates towards an aperture plane located in a free space beyond the outline of the feed element at the front of the array. ### Claim 5 (depends on 2) The phased antenna array device according to claim 2, further comprising: a first interconnection structure positioned behind the one or more substrates and connecting the synchronization bus Bs between the NCO and plurality of IC chips so as to maintain phase stability of the synchronization signals fed into each of the one or more substrates. ### Claim 6 (depends on 1) The phased antenna array device according to claim 1, further comprising: at least one interposer embedded between the antenna elements and the OMTs, the interposer being arranged to perform frequency separation/discrimination between reception and transmission bands. ### Claim 7 (depends on 4) The phased antenna array device according to claim 4, further comprising: at least one interposer embedded between the synchronization bus and an interconnection structure, the interposer being arranged to connect at least one die to the synchronization bus. ### Claim 8 (depends on 3) The phased antenna array device according to claim 3, further comprising: a metamaterial structure formed in a superstrate, the metamaterial structure being arranged to control boundary conditions at a surface of the superstrate presented to the one or more substrates. ### Claim 9 (depends on 3) The phased antenna array device according to claim 3, wherein at least one component comprises a functional material, preferably a ceramic, ferrite or nano material. ### Claim 10 (depends on 7) The phased antenna array device according to claim 7, wherein at least one component of the phased antenna array device is arranged to correct a phase of phase-shifted signals, and/or to prevent a mode conversion of the phase-shifted signals. ### Claim 11 (depends on 6) The phased antenna array device according to claim 6, wherein at least one component of the phased antenna array device is arranged to support propagation mode transformations of phase shifted-signals and/or to create left handed propagation properties for the phase shifted-signals. ### Claim 12 (depends on 1) The phased antenna array device according to claim 1, further comprising: at least one further layer configured to isolate antenna elements from each other at radio frequencies, or to isolate the phased antenna array device from an external application board or electronic equipment attached thereto in use. ### Claim 13 (depends on 1) The phased antenna array device according to claim 1, further comprising: at least one field effect transistor arranged to amplify signals transmitted at radio frequency within the phased antenna array device. ### Claim 14 (depends on 1) The phased antenna array device according to claim 1, formed by a reconstituted wafer process or an embedded wafer level package process. ### Claim 15 (depends on 1) The phased antenna array device according to claim 1, the phased antenna array device being formed on a full reticle wafer.