# US 12,015,099 B2 · Semiconductor sensor and methods thereof

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- Number: US 12,015,099 B2
- Document ID: US12015099B2
- Status: Granted
- Kind: B2
- Application number: 17/337,265
- Filed: 2021-06-02
- Published: 2022-02-03
- Granted: 2024-06-18
- Earliest claimed: 2020-08-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yin-Kai Liao; Jen-Cheng Liu; Kuan-Chieh Huang; Chih-Ming Hung; Yi-Shin Chu; Hsiang-Lin Chen; Sin-Yi Jiang
- Web page: https://patentgrep.com/patent/US12015099B2

## CPC

- H10F 71/121: {The active layers comprising only Group IV materials}
- H10F 30/223: the potential barrier being a PIN barrier
- H10F 39/014: {of CMOS image sensors}
- H10F 39/026: {Wafer-level processing}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/811: {Interconnections}
- H10F 71/1212: {consisting of germanium}
- H10F 77/1223: characterised by the dopants
- H10F 77/933: {for devices having potential barriers}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.

## Claims

### Claim 1

A method of fabricating a semiconductor device, comprising:
providing a substrate including a pixel region and a logic region;
forming a trench within the pixel region;
after forming the trench, forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench;
forming an undoped germanium layer within the trench and over the doped semiconductor layer, wherein the undoped germanium layer substantially fills the trench; and
after forming the undoped germanium layer, forming an optical sensor within the undoped germanium layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the doped semiconductor layer includes performing an ion implantation process into the sidewalls and the bottom surface of the trench.

### Claim 3 (depends on 2)

The method of claim 2, further comprising prior to performing the ion implantation process, forming an oxide layer over the sidewalls and the bottom surface of the trench.

### Claim 4 (depends on 3)

The method of claim 3, further comprising prior to forming the undoped germanium layer, removing the oxide layer.

### Claim 5 (depends on 2)

The method of claim 2, wherein the ion implantation process forms a doped silicon (Si) layer along the sidewalk and the bottom surface of the trench.

### Claim 6 (depends on 1)

The method of claim 1, wherein the forming the doped semiconductor layer includes epitaxially growing a doped Si layer along the sidewalls and the bottom surface of the trench.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming the doped semiconductor layer includes epitaxially growing a doped germanium (Ge) layer along the sidewalls and the bottom surface of the trench.

### Claim 8 (depends on 1)

The method of claim 1, wherein the doped semiconductor layer includes at least one of a P-type material and Group VIIA material.

### Claim 9 (depends on 8)

The method of claim 8, wherein the P-type material includes boron (B), aluminum (Al), gallium (Ga), indium (In) and BF2.

### Claim 10 (depends on 8)

The method of claim 8, wherein the Group VIIA material includes fluorine (F), chlorine(Cl), and bromine(Br).

### Claim 11

A method, comprising:
providing a substrate;
forming a germanium layer over the substrate;
after forming the germanium layer, forming a doped layer along a bottom portion of the germanium layer, the doped layer spaced a distance from an interface between the germanium layer and the substrate, wherein the forming the doped layer includes performing an ion implantation process into the germanium layer; and
after forming the doped layer, forming an optical sensor within the germanium layer.

### Claim 12 (depends on 11)

The method of claim 11, further comprising prior to performing the ion implantation process, forming an oxide layer over germanium layer.

### Claim 13 (depends on 12)

The method of claim 12, further comprising prior to forming the optical sensor, removing the oxide layer.

### Claim 14 (depends on 11)

The method of claim 11, further comprising after forming the optical sensor, forming contacts and multilayer interconnect features coupled to the optical sensor.

### Claim 15 (depends on 14)

The method of claim 14, further comprising after forming the contacts and multilayer interconnect features, bonding the substrate including the optical sensor to a separate device substrate.

### Claim 16 (depends on 11)

The method of claim 11, wherein the doped layer includes at least one of a P-type material and Group VIIA material.

### Claim 17 (depends on 11)

The method of claim 11, further comprising prior to forming the germanium layer, forming a trench within a pixel region of the substrate and forming the germanium layer within the trench.

### Claim 18

A semiconductor device, comprising:
a silicon (Si) substrate including a pixel region and a logic region adjacent to the pixel region;
a germanium (Ge) layer formed in a trench within the Si substrate disposed within the pixel region, wherein a Ge—Si interface is defined along sidewalls and along a bottom surface of the trench, and wherein a sensor is disposed within the Ge laver, the sensor including an anode and a cathode embedded within the Ge layer; and
a doped region separate from the anode and the cathode, wherein the doped region is disposed proximate to, and spaced a distance from a portion of the Ge—Si interface defined along the bottom surface of the trench, and wherein the doped region substantially blocks electrons within the Si substrate from entering the Ge layer.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the doped region is disposed on a germanium side of the Ge—Si interface or on a silicon side of the Ge—Si interface.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the doped region includes at least one of a P-type material and Group VIIA material, wherein the P-type material includes boron (B), aluminum (Al), gallium (Ga), indium (In) and BF2, and wherein the Group VIIA material includes fluorine (F), chlorine(Cl), and bromine(Br).