# US 12,015,089 B2 · Transistors comprising two-dimensional materials and related memory cells and electronic devices

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- Number: US 12,015,089 B2
- Document ID: US12015089B2
- Status: Granted
- Kind: B2
- Application number: 17/447,393
- Filed: 2021-09-10
- Published: 2021-12-30
- Granted: 2024-06-18
- Earliest claimed: 2018-08-27
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Witold Kula; Gurtej S. Sandhu; John A. Smythe
- Web page: https://patentgrep.com/patent/US12015089B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/477: {Vertical HEMTs or vertical HHMTs}
- H10D 30/6733: {Multi-gate TFTs}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 62/882: {Graphene}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/3238: {being insulating materials}
- H10P 14/3436: {being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.

## Claims

### Claim 1

A transistor, comprising:
a channel comprising a two-dimensional material directly laterally adjacent to a seed material, the channel oriented perpendicular to a base material, a width of the seed material laterally adjacent to the channel greater than a width of the channel;
a gate dielectric directly adjacent to the two-dimensional material on a side of the channel opposite the seed material, a horizontally-oriented portion of the two-dimensional material vertically underling the gate dielectric, and an outer sidewall of the gate dielectric and an outermost lateral edge of the horizontally-oriented portion of the channel substantially vertically aligned with one another; and
a gate adjacent to the gate dielectric.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the channel exhibits an L-shape in cross-section, a first portion of the channel directly overlying the base material and a second portion of the channel vertically adjacent to the first portion and oriented perpendicular to the base material.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein the base material comprises a metal vertically underlying the channel.

### Claim 4 (depends on 3)

The transistor of claim 3, wherein the channel directly contacts the metal.

### Claim 5

A transistor, comprising:
a channel comprising a two-dimensional material oriented perpendicular to a base material, the two-dimensional material comprising a transition metal dichalcogenide, graphene, graphene oxide, stanene, phosphorene, hexagonal boron nitride, borophene, silicone, graphyne, germanene, germanane, a 2D supracrystal, or a combination thereof;
a gate dielectric adjacent to the two-dimensional material, an upper surface of the gate dielectric substantially coplanar with an upper surface of the channel, a horizontally-oriented portion of the two-dimensional material vertically underling the gate dielectric, and an outer sidewall of the gate dielectric and an outermost lateral edge of the horizontally-oriented portion of the channel substantially vertically aligned with one another; and
a gate adjacent to the gate dielectric.

### Claim 6 (depends on 5)

The transistor of claim 5, wherein the two-dimensional material comprises a vertically-oriented portion and the horizontally-oriented portion vertically underlying the vertically-oriented portion, the horizontally-oriented portion extending horizontally beyond an outermost lateral edge of the vertically-oriented portion and directly contacting the base material.

### Claim 7 (depends on 5)

The transistor of claim 5, wherein the gate is laterally adjacent to the channel.

### Claim 8 (depends on 5)

The transistor of claim 5, further comprising another dielectric material directly laterally adjacent to the two-dimensional material, the another dielectric material directly vertically adjacent to a metal of the base material.

### Claim 9 (depends on 5)

The transistor of claim 5, wherein the two-dimensional material comprises molybdenum sulfide (MoS2), molybdenum selenide (MoSe2), molybdenum telluride (MoTe2), tungsten sulfide (WS2), tungsten telluride (WTe2), or a combination thereof.

### Claim 10

A memory cell, comprising:
one or more transistors, at least one of the transistors comprising:
an L-shaped channel comprising a two-dimensional material;
an insulative material directly laterally adjacent to the L-shaped channel, the L-shaped channel comprising a continuously vertical sidewall along an entire length of the insulative material;
a gate dielectric adjacent to the L-shaped channel, an upper surface of the gate dielectric substantially coplanar with an upper surface of the L-shaped channel, and a lower surface of the gate dielectric directly abutting an upper surface of a portion of the L-shaped channel along a horizontal interface therebetween; and
a gate adjacent to the gate dielectric; and
at least one capacitor in operative communication with the at least one transistor.

### Claim 11 (depends on 10)

The memory cell of claim 10, wherein the two-dimensional material comprises a crystalline material.

### Claim 12 (depends on 10)

The memory cell of claim 10, wherein the two-dimensional material comprises a transition metal dichalcogenide, graphene, graphene oxide, stanene, phosphorene, hexagonal boron nitride, borophene, silicone, graphyne, germanene, germanane, a 2D supracrystal, or a combination thereof.

### Claim 13 (depends on 10)

The memory cell of claim 10, wherein the two-dimensional material exhibits a cylindrical shape.

### Claim 14 (depends on 10)

The memory cell of claim 10, wherein the two-dimensional material surrounds the insulative material.

### Claim 15 (depends on 10)

The memory cell of claim 10, wherein the insulative material comprises gallium nitride, aluminum oxide, aluminum nitride, boron nitride, graphene, or a combination thereof.

### Claim 16

An electronic device, comprising:
an array of memory cells, one or more of the memory cells comprising:
transistors, one or more of the transistors comprising:
an L-shaped portion of a two-dimensional material exhibiting a width of from about one monolayer of atoms to about three monolayers of atoms;
a dielectric material adjacent to the L-shaped portion of the two-dimensional material;
a gate dielectric laterally adjacent to the L-shaped portion of the two-dimensional material, upper surfaces of the two-dimensional material, the dielectric material, and the gate dielectric substantially coplanar with one another; and
a gate adjacent to the gate dielectric; and
capacitors in operative communication with the transistors.

### Claim 17 (depends on 16)

The electronic device of claim 16, wherein the two-dimensional material comprises molybdenum sulfide (MoS2), molybdenum selenide (MoSe2), molybdenum telluride (MoTe2), tungsten sulfide (WS2), tungsten selenide (WSe2), tungsten telluride (WTe2), niobium sulfide (NbS2), niobium selenide (NbSe2), niobium telluride (NbTe2), zirconium sulfide (ZrS2), zirconium selenide (ZrSe2), zirconium telluride (ZrTe2), hafnium sulfide (HfS2), hafnium selenide (HfSe2), hafnium telluride (ZrTe2), rhenium sulfide (ReS2), rhenium selenide (ReSe2), rhenium telluride (ReTe2), or a combination thereof.

### Claim 18 (depends on 16)

The electronic device of claim 16, wherein the gate is laterally adjacent to the L-shaped portion of the two-dimensional material.

### Claim 19 (depends on 16)

The electronic device of claim 16, wherein the L-shaped portion is laterally adjacent to and in direct contact with a sidewall of the dielectric material.