# US 12,015,087 B2 · Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

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- Number: US 12,015,087 B2
- Document ID: US12015087B2
- Status: Granted
- Kind: B2
- Application number: 17/956,763
- Filed: 2022-09-29
- Published: 2023-01-19
- Granted: 2024-06-18
- Earliest claimed: 2014-12-12
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Bernhard Sell
- Web page: https://patentgrep.com/patent/US12015087B2

## CPC

- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/36: {the transistor being a FinFET}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6213: {having rounded corners}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 50/642: {Chemical etching}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor body above a substrate;
a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack, a first source or drain region in the semiconductor body at a first side of the gate electrode stack, and a second source or drain region in the semiconductor body at a second side of the gate electrode stack, the second side opposite the first side;
a first sidewall spacer adjacent to the first side of the gate electrode stack and over the first source or drain region, the first source or drain region having a width adjacent to the channel region and beneath the first sidewall spacer, the width greater than a width of the channel region of the semiconductor body, wherein the width of the first source or drain region is approximately 6-40% greater than the width of the channel region; and
a second sidewall spacer adjacent to the second side of the gate electrode stack and over the second source or drain region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the width of the first source or drain region is approximately 2-4 nanometers greater than the width of the channel region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the width of the channel region is in a center of the channel region.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second source or drain region has a width adjacent to the channel region and beneath the second sidewall spacer, the width greater than the width of the channel region of the semiconductor body.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor body has a width under a bottom of the gate electrode stack that is greater than a width of the semiconductor body at a location adjacent to the gate electrode stack.

### Claim 6

A semiconductor device, comprising:
a semiconductor body above a substrate;
a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack, a first source or drain region in the semiconductor body at a first side of the gate electrode stack, and a second source or drain region in the semiconductor body at a second side of the gate electrode stack, the second side opposite the first side;
a first sidewall spacer adjacent to the first side of the gate electrode stack and over a first portion of the first source or drain region, wherein a second portion of the first source or drain region extends beyond the first sidewall spacer, the first portion of the first source or drain region having a width adjacent to the second portion of the first source or drain region and beneath the first sidewall spacer, the width greater than a width of the channel region of the semiconductor body, wherein the width of the first portion of the first source or drain region is approximately 6-40% greater than the width of the channel region; and
a second sidewall spacer adjacent to the second side of the gate electrode stack and over the second source or drain region.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the width of the first portion of the first source or drain region is approximately 2-4 nanometers greater than the width of the channel region.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the width of the channel region is in a center of the channel region.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the second portion of the first source or drain region has a width greater than the width of the first portion of the first source or drain region.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein the second portion of the first source or drain region has a width the same as the width of the first portion of the first source or drain region.

### Claim 11

A method of fabricating a semiconductor device, the method comprising:
forming a semiconductor body above a substrate;
forming a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack, a first source or drain region in the semiconductor body at a first side of the gate electrode stack, and a second source or drain region in the semiconductor body at a second side of the gate electrode stack, the second side opposite the first side;
forming a first sidewall spacer adjacent to the first side of the gate electrode stack and over the first source or drain region, the first source or drain region having a width adjacent to the channel region and beneath the first sidewall spacer, the width greater than a width of the channel region of the semiconductor body, wherein the width of the first source or drain region is approximately 6-40% greater than the width of the channel region; and
forming a second sidewall spacer adjacent to the second side of the gate electrode stack and over the second source or drain region.

### Claim 12 (depends on 11)

The method of claim 11, wherein the width of the first source or drain region is approximately 2-4 nanometers greater than the width of the channel region.

### Claim 13 (depends on 11)

The method of claim 11, wherein the width of the channel region is in a center of the channel region.

### Claim 14 (depends on 11)

The method of claim 11, wherein the second source or drain region has a width adjacent to the channel region and beneath the second sidewall spacer, the width greater than the width of the channel region of the semiconductor body.

### Claim 15

A semiconductor device, comprising:
a semiconductor body above a substrate;
a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack, a first source or drain region in the semiconductor body at a first side of the gate electrode stack, and a second source or drain region in the semiconductor body at a second side of the gate electrode stack, the second side opposite the first side;
a first sidewall spacer adjacent to the first side of the gate electrode stack and over the first source or drain region, the first source or drain region having a width adjacent to the channel region and beneath the first sidewall spacer, the width greater than a width of the channel region of the semiconductor body, wherein the width of the first source or drain region is approximately 2-4 nanometers greater than the width of the channel region; and
a second sidewall spacer adjacent to the second side of the gate electrode stack and over the second source or drain region.

### Claim 16

A semiconductor device, comprising:
a semiconductor body above a substrate;
a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack, a first source or drain region in the semiconductor body at a first side of the gate electrode stack, and a second source or drain region in the semiconductor body at a second side of the gate electrode stack, the second side opposite the first side;
a first sidewall spacer adjacent to the first side of the gate electrode stack and over a first portion of the first source or drain region, wherein a second portion of the first source or drain region extends beyond the first sidewall spacer, the first portion of the first source or drain region having a width adjacent to the second portion of the first source or drain region and beneath the first sidewall spacer, the width greater than a width of the channel region of the semiconductor body, wherein the width of the first portion of the first source or drain region is approximately 2-4 nanometers greater than the width of the channel region; and
a second sidewall spacer adjacent to the second side of the gate electrode stack and over the second source or drain region.

### Claim 17

A method of fabricating a semiconductor device, the method comprising:
forming a semiconductor body above a substrate;
forming a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack, a first source or drain region in the semiconductor body at a first side of the gate electrode stack, and a second source or drain region in the semiconductor body at a second side of the gate electrode stack, the second side opposite the first side;
forming a first sidewall spacer adjacent to the first side of the gate electrode stack and over the first source or drain region, the first source or drain region having a width adjacent to the channel region and beneath the first sidewall spacer, the width greater than a width of the channel region of the semiconductor body, wherein the width of the first source or drain region is approximately 2-4 nanometers greater than the width of the channel region; and
forming a second sidewall spacer adjacent to the second side of the gate electrode stack and over the second source or drain region.